Samsung KM48S8030CT-G-FL, KM48S8030CT-G-F8, KM48S8030CT-G-F7, KM48S8030CT-G-F10, KM48S8030CT-G-FH Datasheet

	Preliminary
KM48S8030C	CMOS SDRAM

Revision History

Revision 1 (May 1998)

- ICC2N value (10mA) is changed to 12mA.

Revision .2 (June 1998)

- tSH (-10 binning) is revised.

REV. 2 June '98

	Preliminary
KM48S8030C	CMOS SDRAM

2M x 8Bit x 4 Banks Synchronous DRAM

FEATURES

•JEDEC standard 3.3V power supply

•LVTTL compatible with multiplexed address

•Four banks operation

•MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

•All inputs are sampled at the positive going edge of the system clock

•Burst read single-bit write operation

•DQM for masking

•Auto & self refresh

•64ms refresh period (4K Cycle)

GENERAL DESCRIPTION

The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

	Part No.	Max Freq.	Interface	Package
	KM48S8030CT-G/F7	143MHz
	KM48S8030CT-G/F8	125MHz		54
	KM48S8030CT-G/FH	100MHz	LVTTL
				TSOP(II)
	KM48S8030CT-G/FL	100MHz
	KM48S8030CT-G/F10	100MHz

FUNCTIONAL BLOCK DIAGRAM

							Data Input Register
		Bank Select
	Address		CounterRefresh	BufferRow	DecoderRow			2M x 8
								2M x 8
								2M x 8
CLK								2M x 8
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM

AMP Sense

	I/O					LWE
	Control					LDQM
	Output					DQi
	Buffer

LDQM

*Samsung Electronics reserves the right to change products or specification without notice.

REV. 2 June '98

Preliminary

KM48S8030C

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

1

54

VSS

DQ0

2

53

DQ7

VDDQ

3

52

VSSQ

N.C

4

51

N.C

DQ1

5

50

DQ6

VSSQ

6

49

VDDQ

N.C

7

48

N.C

DQ2

8

47

DQ5

VDDQ

9

46

VSSQ

N.C

10

45

N.C

DQ3

11

44

DQ4

VSSQ

12

43

VDDQ

N.C

13

42

N.C

VDD

14

41

VSS

N.C

15

40

N.C/RFU

WE

16

39

DQM

CAS

17

38

CLK

RAS

18

37

CKE

CS

19

36

N.C

BA0

20

35

A11

BA1

21

34

A9

A10/AP

22

33

A8

A0

23

32

A7

A1

24

31

A6

A2

25

30

A5

54Pin TSOP (II)

A3

26

29

A4

(400mil x 875mil)

VDD

27

28

VSS

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CS

Chip select

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE

Clock enable

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA 0 ~ RA11, Column address : CA 0 ~ CA8

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with

low.

RAS

RAS

Row address strobe

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with

low.

CAS

CAS

Column address strobe

Enables column access.

Enables write operation and row precharge.

WE

Write enable

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ 7

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

This pin is recommended to be left No Connection on the device.

/reserved for future use

REV. 2 June '98

				Preliminary
KM48S8030C				CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol	Value		Unit
Voltage on any pin relative to Vss		VIN, VOUT	-1.0 ~ 4.6		V
Voltage on VDD supply relative to Vss		VDD, VDDQ	-1.0 ~ 4.6		V
Storage temperature		TSTG	-55 ~ +150		°C
Power dissipation		PD	1		W
Short circuit current		IOS	50		mA

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit	Note
Supply voltage	VDD, VDDQ	3.0	3.3	3.6	V
Input logic high voltage	VIH	2.0	3.0	VDDQ+0.3	V	1
Input logic low voltage	VIL	-0.3	0	0.8	V	2
Output logic high voltage	VOH	2.4	-	-	V	IOH = -2mA
Output logic low voltage	VOL	-	-	0.4	V	IOL = 2mA
Input leakage current (Inputs)	IIL	-1	-	1	uA	3
Input leakage current (I/O pins)	IIL	-1.5	-	1.5	uA	3,4

Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2.VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3.Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin

Symbol

Min

Max

Unit

Clock

CCLK

2.5

4.0

pF

CKE, DQM

CIN

2.5

5.0

pF

RAS,

CAS,

WE,

CS,

Address

CADD

2.5

5.0

pF

DQ0 ~ DQ7

COUT

4.0

6.5

pF

REV. 2 June '98