Samsung KM6264BLP-7L, KM6264BLP-7, KM6264BLP-10L, KM6264BLP-10, KM6264BLGI-10L Datasheet

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Samsung KM6264BLP-7L, KM6264BLP-7, KM6264BLP-10L, KM6264BLP-10, KM6264BLGI-10L Datasheet

KM6264B Family

 

 

CMOS SRAM

8Kx8 bit Low Power CMOS Static RAM

 

 

 

 

FEATURE SUMMARY

 

GENERAL DESCRIPTION

 

Process Technology : CMOS

 

The KM6264B family is fabricated by SAMSUNG's

 

Organization : 8K x 8

 

advanced CMOS process technology. The family

 

Power Supply Voltage : Single 5V ± 10%

can support various operating temperature ranges

 

Low Data Retention Voltage : 2V(Min)

and has various package types for user flexibility of

 

Three state output and TTL Compatible

system design. The family also support low data

 

Package Type : JEDEC Standard

 

retention voltage for battery back-up operations with

 

 

28-DIP, 28-SOP

 

low data retention current.

 

PRODUCT FAMILY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Product

 

Operating

Speed

PKG Type

Power Dissipation

 

 

Family

 

Temperature

Standby(Isb1, Max)

Operating(Icc2)

 

 

 

 

 

 

 

KM6264BL

 

Commercial

70/100/120ns

28-DIP, 28-SOP

100uA

 

 

 

KM6264BL-L

 

(0~70 °C)

10uA

 

 

 

 

 

 

 

 

 

KM6264BLE

 

Extended

100*ns

28-SOP

100uA

55mA

 

 

KM6264BLE-L

 

(-25~-85 °C)

50uA

 

 

 

 

 

 

 

 

 

 

 

 

KM6264BLI

 

Industrial

100*ns

28-SOP

100uA

 

 

 

KM6264BLI-L

 

(-40~85 °C)

50uA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

* measured with 30pF test load

PIN DESCRIPTION

 

 

 

 

 

 

 

 

N.C

 

1

28

 

Vcc

 

 

A12

 

2

27

 

/WE

 

 

A7

 

3

26

 

CS2

 

 

A6

 

4

25

 

A8

 

 

A5

 

5

24

 

A9

 

 

A4

 

6

23

 

A11

 

 

A3

 

7

28-Pin DIP 22

 

/OE

 

 

 

 

A2

 

8

28-Pin SOP 21

 

A10

 

 

 

 

 

A1

 

9

20

 

/CS1

A0

 

10

19

 

I/O8

 

 

I/O1

 

11

18

 

I/O7

 

 

I/O2

 

12

17

 

I/O6

 

 

I/O3

 

13

16

 

I/O5

 

 

Vss

 

14

15

 

I/O4

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL BLOCK DIAGRAM

Y-Decoder

A0~A12

Decoder-X

I/O1~8

Cell Array

I/O Buffer

Logic Control

/CS1, CS2 /WE, /OE

Pin Name

Function

A0~A12

Address Inputs

/WE

Write Enable Input

/CS1, CS2

Chip Select Input

/OE

Output Enable Input

I/O1~I/O8

Data Input/Output

Vcc

Power(5V)

 

 

Vss

Ground

 

 

N.C

No Connection

 

 

1

Revision. 0.0

Auust. 1996

ELECTRONICS

 

KM6264B Family

 

 

 

 

CMOS SRAM

 

PRODUCT LIST & ORDERING INFORMATION

 

 

 

 

 

PRODUCT LIST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Commercial Temp Products

Extended Temp Products

Industrial Temp Products

 

 

(0~70 °C)

(-25~85 °C)

 

(-40~85 °C)

 

 

 

 

 

 

 

 

 

 

Part Name

 

Function

Part Name

Function

Part Name

 

Function

 

 

 

 

 

 

 

 

 

 

KM6264BLP-7

 

28-DIP, 70ns, L-pwr

KM6264BLGE-10

28-SOP, 100ns, L-pwr

KM6264BLGI-10

 

28-SOP, 100ns, L-pwr

 

KM6264BLP-7L

 

28-DIP, 70ns, , LL-pwr

KM6264BLGE-10L

28-SOP, 100ns, LL-pwr

KM6264BLGI-10L

 

28-SOP, 100ns, LL-pwr

 

KM6264BLP-10

 

28-DIP, 100ns, , L-pwr

 

 

 

 

 

 

 

KM6264BLP-10L

 

28-DIP, 100ns, LL-pwr

 

 

 

 

 

 

 

KM6264BLP-12

 

28-DIP, 120ns, , L-pwr

 

 

 

 

 

 

 

KM6264BLP-12L

 

28-DIP, 120ns, LL-pwr

 

 

 

 

 

 

 

KM6264BLG-7

 

28-SOP, 70ns, L-pwr

 

 

 

 

 

 

 

KM6264BLG-7L

 

28-SOP, 70ns, LL-pwr

 

 

 

 

 

 

 

KM6264BLG-10

 

28-SOP, 100ns, L-pwr

 

 

 

 

 

 

 

KM6264BLG-10L

 

28-SOP, 100ns, LL-pwr

 

 

 

 

 

 

 

KM6264BLG-12

 

28-SOP, 120ns, L-pwr

 

 

 

 

 

 

 

KM6264BLG-12L

 

28-SOP, 120ns, LL-pwr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ORDERING INFORMATION

K M6 2 X 64 B X X XX - XX X

L-Low Low Power, Blank-Low Power or High Power

Access Time : 7=70ns, 10=100ns, 12=120ns

Operating Temperature :

I=Industrial, E=Extended, Blank=Commercial

Package Type : G=SOP, P=DIP,

L-Low Power or Low Low Power, Blank-High Power

Die Version : B=3rd generation

Density : 64=64K bit

Blank=5V

Organization : 2= x8

SEC Standard SRAM

2

Revision. 0.0

Auust. 1996

ELECTRONICS

KM6264B Family

 

 

 

CMOS SRAM

ABSOLUTE MAXIMUM RATINGS *

 

 

 

 

 

 

 

 

 

 

 

 

Item

Symbol

Ratings

Unit

Remark

 

 

Voltage on any pin relative to Vss

Vin, Vout

-0.5 to Vcc+0.5

V

-

 

 

Voltage on Vcc supply relative to Vss

Vcc

-0.5 to 7.0

V

-

 

 

Power Dissipation

Pd

1.0

W

-

 

 

Storage temperature

Tstg

-65 to 150

°C

-

 

 

Operating Temperature

Ta

0 to 70

°C

KM6264BL/L-L

 

 

 

 

-25 to 85

°C

KM6264BLE/LE-L

 

 

 

 

-40 to 85

°C

KM6264BLI/LI-L

 

 

Soldering temperature and time

Tsolder

260 °C, 10sec(Lead Only)

-

-

 

 

 

 

 

 

 

 

* Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS*

Item

Symbol

Min

Typ**

Max

Unit

Supply voltage

Vcc

4.5

5.0

5.5

V

Ground

Vss

0

0

0

V

Input high voltage

Vih

2.2

-

Vcc+0.5

V

Input low voltage

Vil

-0.5***

-

0.8

V

*1) Commercial Product : Ta=0 to 70 ° C, unless otherwise specified

2)Extended Product : Ta=-25 to 85 ° C, unless otherwise specified

3)Industrial Product : Ta=-40 to 85 ° C, unless otherwise specified

**Ta=25 ° C

***Vil(min)=-3.0V for ¡ Â50ns pulse

CAPACITANCE * (f=1MHz, Ta=25 °C)

Item

Symbol

Test Condition

Min

Max

Unit

Input capacitance

Cin

Vin=0V

-

6

pF

Input/Output capacitance

Cio

Vio=0V

-

8

pF

 

 

 

 

 

 

* Capacitance is sampled not 100% tested

3

Revision. 0.0

Auust. 1996

ELECTRONICS

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