Samsung KM44C4105CSL-6, KM44C4105CSL-5, KM44C4105CS-6, KM44C4105CKL-5, KM44C4105CK-6 Datasheet

KM44C4005C, KM44C4105C

CMOS DRAM

4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out

DESCRIPTION

This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.

This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high bandwidth, low power consumption and high reliability.

FEATURES

•Part Identification

-KM44C4005C/C-L (5V, 4K Ref.)

-KM44C4105C/C-L (5V, 2K Ref.)

•Active Power Dissipation

			Unit : mW
Speed		Refresh Cycle
	4K		2K
-5	495		605
-6	440		550

•Extended Data Out mode operation

(Fast Page Mode with Extended Data Out)

•Four separate CAS pins provide for separate I/O operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•Fast parallel test mode capability

•TTL compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic SOJ and TSOP(II) packages

•Single +5V±10% power supply

•	Refresh Cycles
	Part			Refresh					Refresh period
	NO.			cycle			Normal				L-ver
	C4005C			4K				64ms			128ms
	C4105C			2K				32ms
•	Performance Range
Speed			tRAC			tCAC			tRC		tHPC
	-5		50ns			13ns			84ns		20ns
	-6		60ns			15ns			104ns		25ns

FUNCTIONAL BLOCK DIAGRAM

RAS

Control

Vcc

CAS0 - 3

Vss

W

Clocks

VBB Generator

				Data in
	Refresh Timer	Row Decoder		Buffer
	Refresh Control		I/O
			&		DQ0
		Memory Array
			Amps
					to
	Refresh Counter	4,194,304 x 4
					DQ3
		Cells	Sense
A0-A11	Row Address Buffer
(A0 - A10) *1				Data out
A0 - A9
	Col. Address Buffer	Column Decoder		Buffer	OE
(A0 - A10)
	*1
Note) *1 : 2K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

KM44C4005C, KM44C4105C

CMOS DRAM

PIN CONFIGURATION (Top Views)

VCC

DQ0

DQ1 W RAS

*A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC

•KM44C40(1)05CK				•KM44C40(1)05CS
1	28	VSS	VCC	1	28	VSS
2	27	DQ3	DQ0	2	27	DQ3
3	26	DQ2	DQ1	3	26	DQ2
4	25	CAS3	W	4	25	CAS3
5	24	OE	RAS	5	24	OE
6	23	A9	*A11(N.C)	6	23	A9
7	22	CAS2	CAS0	7	22	CAS2
8	21	N.C	CAS1	8	21	N.C
9	20	A8	A10	9	20	A8
10	19	A7	A0	10	19	A7
11	18	A6	A1	11	18	A6
12	17	A5	A2	12	17	A5
13	16	A4	A3	13	16	A4
14	15	VSS	VCC	14	15	VSS

*A11 is N.C for KM44C4105C(5V, 2K Ref. product)

K : 300mil 28 SOJ

S : 300mil 28 TSOP II

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A10

Address Inputs (2K Product)

DQ0 - 3

Data In/Out

VSS

Ground

Row Address Strobe

RAS

Column Address Strobe

CAS0~CAS3

Read/Write Input

W

Data Output Enable

OE

VCC

Power(+5.0V)

N.C

No Connection

KM44C4005C, KM44C4105C						CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol	Rating				Units
Voltage on any pin relative to VSS		VIN,VOUT	-1.0	to	+7.0		V
Voltage on VCC supply relative to VSS		VCC	-1.0	to	+7.0		V
Storage Temperature		Tstg	-55 to +150				°C
Power Dissipation		PD		1			W
Short Circuit Output Current		IOS		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol		Min	Typ	Max	Units
Supply Voltage		VCC		4.5	5.0	5.5	V
Ground		VSS		0	0	0	V
Input High Voltage		VIH		2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL		-1.0*2	-	0.8	V
*1	: VCC+2.0V/20ns, Pulse width is measured at VCC
*2	: -2.0/20ns, Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

		Parameter	Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,		II(L)	-5	5	uA
	all other input pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-5mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=4.2mA)		VOL	-	0.4	V

KM44C4005C, KM44C4105C							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				KM44C4005C		KM44C4105C
		-5		90		110		mA
ICC1	Don′t care							mA
		-6		80		100
								mA
ICC2	Normal	Don′t care		2		2		mA
	L			1		1		mA
		-5		90		110		mA
ICC3	Don′t care							mA
		-6		80		100
								mA
		-5		80		90		mA
ICC4	Don′t care							mA
		-6		70		80
								mA
ICC5	Normal	Don′t care		1		1		mA
	L			250		250		uA
		-5		90		110		mA
ICC6	Don′t care							mA
		-6		80		100
								mA
ICC7	L	Don′t care		300		300		uA
ICCS	L	Don′t care		250		250		uA

ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)

ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,

DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,

DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

KM44C4005C, KM44C4105C

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

CASx, W, OE]

Output capacitance [DQ0 - DQ3]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Parameter

Symbol

-5

-6

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

tRC

84

104

ns

Read-modify-write cycle time

tRWC

106

140

ns

Access time from

tRAC

50

60

ns

3,4,10

RAS

Access time from

tCAC

13

15

ns

3,4,5,20

CAS

Access time from column address

tAA

25

30

ns

3,10

to output in Low-Z

tCLZ

3

3

ns

3,20

CAS

Output buffer turn-off delay from

tCEZ

3

13

3

15

ns

6,13

CAS

to output in Low-Z

tOLZ

3

3

ns

3

OE

Transition time (rise and fall)

tT

2

50

2

50

ns

2

precharge time

tRP

30

40

ns

RAS

pulse width

tRAS

50

10K

60

10K

ns

RAS

hold time

tRSH

13

15

ns

16

RAS

hold time

tCSH

38

45

ns

19

CAS

pulse width

tCAS

8

10K

10

10K

ns

25

CAS

to

delay time

tRCD

20

37

20

45

ns

4,18

RAS

CAS

to column address delay time

tRAD

15

25

15

30

ns

10

RAS

to

precharge time

tCRP

5

5

ns

17

CAS

RAS

Row address set-up time

tASR

0

0

ns

Row address hold time

tRAH

10

10

ns

Column address set-up time

tASC

0

0

ns

18

Column address hold time

tCAH

8

10

ns

18

Column address to

lead time

tRAL

25

30

ns

RAS

Read command set-up time

tRCS

0

0

ns

Read command hold time referenced to

tRCH

0

0

ns

8,17

CAS

Read command hold time referenced to

tRRH

0

0

ns

8

RAS

Write command hold time

tWCH

10

10

ns

16

Write command pulse width

tWP

10

10

ns

Write command to

lead time

tRWL

13

15

ns

RAS

Write command to

lead time

tCWL

8

10

ns

19

CAS

KM44C4005C, KM44C4105C

CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter

Symbol

-5

-6

Units

Notes

Min

Max

Min

Max

Data set-up time

tDS

0

0

ns

9

Data hold time

tDH

8

10

ns

9

Refresh period (2K, Normal)

tREF

32

32

ms

Refresh period (4K, Normal)

tREF

64

64

ms

Refresh period (L-ver)

tREF

128

128

ms

Write command set-up time

tWCS

0

0

ns

7,18

to

delay time

tCWD

30

34

ns

7,16

CAS

W

to

delay time

tRWD

67

79

ns

7

RAS

W

Column address to

delay time

tAWD

42

49

ns

7

W

precharge to

delay time

tCPWD

47

54

ns

7

CAS

W

set-up time

-before-

refresh)

tCSR

5

5

ns

18

CAS

(CAS

RAS

hold time

-before-

refresh)

tCHR

10

10

ns

17

CAS

(CAS

RAS

to

precharge time

tRPC

5

5

ns

18

RAS

CAS

Access time from

precharge

tCPA

28

35

ns

3,17

CAS

Hyper Page mode cycle time

tHPC

20

24

ns

14,21

Hyper Page read-modify-write cycle time

tHPRWC

62

71

ns

14,21

precharge time (Hyper Page cycle)

tCP

8

10

ns

22

CAS

pulse width (Hyper Page cycle)

tRASP

50

200K

60

200K

ns

RAS

hold time from

precharge

tRHCP

30

35

ns

RAS

CAS

access time

tOEA

13

15

ns

23

OE

to data delay

tOED

13

15

ns

24

OE

Output buffer turn off delay time from

tOEZ

3

13

3

15

ns

6

OE

command hold time

tOEH

13

15

ns

OE

Write command set-up time (Test mode in)

tWTS

10

10

ns

11

Write command hold time (Test mode in)

tWTH

10

10

ns

11

to

precharge time(C

-B-

refresh)

tWRP

10

10

ns

W

RAS

R

to

hold time(C

-B-

refresh)

tWRH

10

10

ns

W

RAS

R

Output data hold time

tDOH

5

5

ns

Output buffer turn off delay from

tREZ

3

13

3

15

ns

6,13

RAS

Output buffer turn off delay from

tWEZ

3

13

3

15

ns

6

W

to data delay

tWED

15

15

ns

W

to

hold time

tOCH

5

5

ns

OE

CAS

hold time to

tCHO

5

5

ns

CAS

OE

precharge time

tOEP

5

5

ns

OE

pulse width (Hyper Page Cycle)

tWPE

5

5

ns

W

-B-

self refresh)

tRASS

100

100

us

27,28,29

RAS

pulse width (C

R

-B-

self refresh)

tRPS

90

110

ns

27,28,29

RAS

precharge time (C

R

tCHS

-50

-50

ns

27,28,29

CAS

hold time (C

-B-R self refresh)

Hold time

low to

high

tCLCH

5

5

ns

15,26

CAS

CAS