Samsung KM68257CP-20, KM68257CP-15, KM68257CLTG-15, KM68257CLP-15, KM68257CLP-12 Datasheet

KM68257C/CL	CMOS SRAM

Document Title

32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial Temperature Range.

Revision History

RevNo.	History	Draft Data	Remark
Rev. 0.0	Initial release with Preliminary.	Apr. 1st, 1994	Preliminary
Rev. 1.0	Release to final Data Sheet.	May 14th,1994	Final
	1. Delete Preliminary
Rev. 2.0	Update A.C parameters	Oct. 4th, 1994	Final
	2.1. Updated A.C parameters

	Items	Previous spec.	Updated spec.
		(12/15/20ns part)	(12/15/20ns part)
	tOE	- / 8/10ns	- / 7 /9 ns
	tCW	- /12/ - ns	- /11/ - ns
	tHZ	8/10/10ns	6/7/8ns
	tOHZ	- / 8 / - ns	- / 7 / - ns
	tDW	- / 9 / - ns	- / 8 / - ns

	2.2. Add Voh1=3.95V with the test condition as Vcc=5V±5% at 25°C
Rev. 3.0	3.1. Add 28-TSOP1 Package.	Feb. 22th, 1996	Final
	3.2. Add L-version.
	3.3. Add Data Rentention Characteristics.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -	Rev 3.0
	February-1996

KM68257C/CL	CMOS SRAM

32K x 8 Bit High-Speed CMOS Static RAM

FEATURES

¡Ü	Fast Access Time 12, 15, 20§À(Max.)
¡Ü	Low Power Dissipation
	Standby (TTL) : 40§Ì(Max.)
	(CMOS) : 2§Ì(Max.)
	0.1§Ì(Max.)- L-ver. only
	Operating KM68257C/CL - 12 : 165§Ì(Max.)
	KM68257C/CL - 15 : 150§Ì(Max.)
	KM68257C/CL - 20 : 140§Ì(Max.)
¡Ü	±
	Single 5.0V 10% Power Supply

¡Ü TTL Compatible Inputs and Outputs ¡Ü I/O Compatible with 3.3V Device

¡Ü Fully Static Operation

- No Clock or Refresh required ¡Ü Three State Outputs

¡Ü Low Data Retention Voltage : 2V(Min.)- L-ver. only ¡Ü Standard Pin Configuration

KM68257C/CLP : 28-DIP-300

KM68257C/CLJ : 28-SOJ-300 KM68257C/CLTG : 28-TSOP1-0813, 4F

FUNCTIONAL BLOCK DIAGRAM

A3				Clk Gen.					Pre-Charge-Circuit
A4
A5							Select
A6										Memory Array
A7							Row			512 Rows
A8										64x8 Columns
A12

	A13
	A14
	I/O1 ~ I/O8	Data	I/O Circuit
		Cont.	Column Select
		CLK
		Gen.
			A0 A1 A2 A9 A10 A11
	CS
	WE
	OE

GENERAL DESCRIPTION

The KM68257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68257C is packaged in a 300 mil 28-pin plastic DIP, SOJ or TSOP1 forward.

PIN CONFIGURATION(Top View)

	OE			1					28							A10
A11				2					27							CS
	A9			3					26							I/O8
	A8			4					25							I/O7
A13				5					24							I/O6
WE				6					23							I/O5
Vcc				7		TSOP1			22							I/O4
A14				8					21							Vss
A12				9					20							I/O3
	A7			10					19							I/O2
	A6			11					18							I/O1
	A5			12					17							A0
	A4			13					16							A1
	A3			14					15							A2
				A14	1				28		Vcc
				A12	2				27		WE
				A7	3				26		A13
				A6							A8
					4				25
				A5							A9
					5				24
				A4							A11
					6				23
				A3
					7	SOJ/DIP			22		OE
				A2							A10
					8				21
				A1
					9				20		CS
				A0							I/O8
					10				19
				I/O1							I/O7
					11				18
				I/O2							I/O6
					12				17
				I/O3							I/O5
					13				16
				Vss							I/O4
					14				15

PIN FUNCTION

Pin Name						Pin Function
A0 - A14						Address Inputs
						Write Enable
	WE
						Chip Select
		CS
						Output Enable
		OE
I/O1 ~ I/O8						Data Inputs/Outputs
VCC						Power(+5.0V)
VSS						Ground

- 2 -	Rev 3.0
	February-1996

KM68257C/CL			CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter	Symbol	Rating	Unit
Voltage on Any Pin Relative to VSS	VIN, VOUT	-0.5 to 7.0	V
Voltage on VCC Supply Relative to VSS	VCC	-0.5 to 7.0	V
Power Dissipation	PD	1.0	W
Storage Temperature	TSTG	-65 to 150	°C
Operating Temperature	TA	0 to 70	°C

* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage	VCC	4.5	5.0	5.5	V
Ground	VSS	0	0	0	V
Input Low Voltage	VIH	2.2	-	VCC+0.5**	V
Input Low Voltage	VIL	-0.5*	-	0.8	V

*VIL(Min) = -2.0(Pulse Width ≤10ns) for I≤20§Ì

**VIH(Max) = VCC+2.0V(Pulse Width ≤10ns) for I≤20§Ì

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

ILI

VIN = VSS to VCC

-2

2

mA

Output Leakage Current

ILO

CS=VIH or OE=VIH or WE=VIL

-2

2

mA

VOUT = VSS to VCC

Min. Cycle, 100% Duty

12ns

-

165

§Ì

Operating Current

ICC

CS=VIL, VIN = VIH or VIL,

15ns

-

150

IOUT=0mA

20ns

-

140

ISB

Min. Cycle,

-

40

§Ì

CS=VIH

Standby Current

f=0MHz,

³VCC-0.2V,

Normal

-

2

ISB1

CS

§Ì

VIN³VCC-0.2V or VIN£0.2V

L-ver

-

0.1

Output Low Voltage Level

VOL

IOL=8mA

-

0.4

V

Output High Voltage Level

VOH

IOH=-4mA

2.4

-

V

VOH1*

IOH1=0.1mA

-

3.95

V

* VCC=5.0V±5% Temp.=25°C

CAPACITANCE*(TA =25°C, f=1.0MHz)

Item	Symbol	Test Conditions	MIN	Max	Unit
Input/Output Capacitance	CI/O	VI/O=0V	-	8	pF
Input Capacitance	CIN	VIN=0V	-	7	pF

* NOTE : Capacitance is sampled and not 100% tested.

- 3 -	Rev 3.0
	February-1996