Samsung K4S643232C-TL55, K4S643232C-TL10, K4S643232C-TC80, K4S643232C-TC70, K4S643232C-TC60 Datasheet

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K4S643232C

CMOS SDRAM

2M x 32 SDRAM

512K x 32bit x 4 Banks Synchronous DRAM LVTTL

Revision 1.1

November 1999

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

REV. 1.1 Nov. '99

K4S643232C

CMOS SDRAM

Revision History

Revision 1.1 (November 17th, 1999)

• Corrected typo in ordering information on page 3

Revision 1.0 (October, 1999)

• Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system

- 2 -

REV. 1.1 Nov. '99

Samsung K4S643232C-TL55, K4S643232C-TL10, K4S643232C-TC80, K4S643232C-TC70, K4S643232C-TC60 Datasheet

K4S643232C

CMOS SDRAM

512K x 32Bit x 4 Banks Synchronous DRAM

FEATURES

3.3V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the system clock

Burst read single-bit write operation

DQM for masking

Auto & self refresh

15.6us refresh duty cycle

GENERAL DESCRIPTION

The K4S643232C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

Part NO.

Max Freq.

Interface

Package

K4S643232C-TC/L55

183MHz

 

 

 

 

 

 

K4S643232C-TC/L60

166MHz

 

86

 

 

LVTTL

K4S643232C-TC/L70

143MHz

TSOP(II)

 

 

 

K4S643232C-TC/L80

125MHz

 

 

 

 

 

 

 

K4S643232C-TC/L10

100MHz

 

 

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

I/O

 

 

LWE

 

 

 

 

Control

 

 

Data Input Register

 

 

 

LDQM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bank Select

 

Address

 

CounterRefresh

BufferRow

DecoderRow

 

 

512K x 32

AMPSense

BufferOutput

 

 

 

 

 

512K x 32

DQi

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512K x 32

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

512K x 32

 

 

 

 

Register

 

LRAS

LCBR

Buffer.Col

 

 

 

 

 

ADD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Decoder

 

 

 

 

 

 

 

 

 

 

Latency & Burst Length

 

 

 

LCKE

 

 

 

 

 

Programming Register

 

 

 

 

 

 

 

 

 

 

 

 

 

LRAS

LCBR

LWE

LCAS

 

LWCBR

 

LDQM

 

 

 

 

 

 

Timing Register

 

 

 

 

 

 

CLK

CKE

 

CS

RAS

CAS

WE

DQM

 

 

 

 

 

 

 

 

 

 

 

* Samsung Electronics reserves the right to

 

 

 

 

 

 

 

 

 

change products or specification without

 

 

 

 

 

 

 

 

 

notice.

 

 

 

 

 

 

 

 

- 3 -

 

 

 

REV. 1.1 Nov. '99

K4S643232C

CMOS SDRAM

PIN CONFIGURATION (Top view)

 

VDD

 

1

86

 

VSS

 

 

 

 

 

 

 

DQ0

 

2

85

 

DQ15

 

 

 

 

 

 

VDDQ

 

3

84

 

VSSQ

 

 

 

 

 

DQ1

 

4

83

 

DQ14

 

 

 

 

 

 

 

DQ2

 

5

82

 

DQ13

 

 

 

 

 

 

VSSQ

 

6

81

 

VDDQ

 

 

 

 

 

DQ3

 

7

80

 

DQ12

 

 

 

 

 

 

 

DQ4

 

8

79

 

DQ11

 

 

 

 

 

 

VDDQ

 

9

78

 

VSSQ

 

 

 

 

 

DQ5

 

10

77

 

DQ10

 

 

 

 

 

 

 

DQ6

 

11

76

 

DQ9

 

 

 

 

 

 

VSSQ

 

12

75

 

VDDQ

 

 

 

 

 

DQ7

 

13

74

 

DQ8

 

 

 

 

 

 

 

N.C

 

14

73

 

N.C

 

 

 

 

 

 

 

VDD

 

15

72

 

VSS

 

 

 

 

 

 

DQM0

 

16

71

 

DQM1

 

 

 

 

 

WE

 

 

17

70

 

N.C

 

 

 

 

 

 

 

CAS

 

18

69

 

N.C

 

 

 

 

 

 

 

RAS

 

19

68

 

CLK

 

 

 

 

 

 

 

CS

 

20

67

 

CKE

 

 

 

 

 

 

 

N.C

 

21

66

 

A9

 

 

 

 

 

 

 

BA0

 

22

65

 

A8

 

 

 

 

 

 

 

BA1

 

23

64

 

A7

 

 

 

 

 

 

A10/AP

 

24

63

 

A6

 

 

 

 

 

A0

 

25

62

 

A5

 

 

 

 

 

 

 

A1

 

26

61

 

A4

 

 

 

 

 

 

 

A2

 

27

60

 

A3

 

 

 

 

 

 

DQM2

 

28

59

 

DQM3

 

 

 

 

 

VDD

 

29

58

 

VSS

 

 

 

 

 

 

 

N.C

 

30

57

 

N.C

 

 

 

 

 

 

DQ16

 

31

56

 

DQ31

 

 

 

 

VSSQ

 

32

55

 

VDDQ

 

 

 

 

DQ17

 

33

54

 

DQ30

 

 

 

 

DQ18

 

34

53

 

DQ29

 

 

 

 

VDDQ

 

35

52

 

VSSQ

 

 

 

 

DQ19

 

36

51

 

DQ28

 

 

 

 

DQ20

 

37

50

 

DQ27

 

 

 

 

VSSQ

 

38

49

 

VDDQ

 

 

 

 

DQ21

 

39

48

 

DQ26

 

 

 

 

DQ22

 

40

47

 

DQ25

 

 

 

 

VDDQ

 

41

46

 

VSSQ

 

 

 

 

DQ23

 

42

45

 

DQ24

 

 

 

 

 

VDD

 

43

44

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch)

- 4 -

REV. 1.1 Nov. '99

K4S643232C

CMOS SDRAM

PIN FUNCTION DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Name

Input Function

 

CLK

System clock

Active on the positive going edge to sample all inputs.

 

 

 

 

 

 

 

 

 

 

 

 

 

Disables or enables device operation by masking or enabling all inputs except

 

CS

Chip select

 

CLK, CKE and DQM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Masks system clock to freeze operation from the next clock cycle.

 

CKE

Clock enable

CKE should be enabled at least one cycle prior to new command.

 

 

 

 

 

 

Disables input buffers for power down mode.

 

 

 

 

 

 

 

 

A0 ~ A10

Address

Row/column addresses are multiplexed on the same pins.

 

Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BA0,1

Bank select address

Selects bank to be activated during row address latch time.

 

Selects bank for read/write during column address latch time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Latches row addresses on the positive going edge of the CLK with RAS low.

 

RAS

Row address strobe

 

Enables row access & precharge.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Latches column addresses on the positive going edge of the CLK with CAS low.

 

CAS

Column address strobe

 

Enables column access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enables write operation and row precharge.

 

WE

Write enable

 

Latches data in starting from CAS, WE active.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQM0 ~ 3

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

 

Blocks data input when DQM active.

 

 

 

 

 

 

 

 

 

 

 

DQ0 ~ 31

Data input/output

Data inputs/outputs are multiplexed on the same pins.

 

 

 

 

 

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

 

 

 

 

 

 

 

 

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

 

immunity.

 

 

 

 

 

 

 

 

 

 

 

NC

No Connection

This pin is recommended to be left No connection on the device.

 

 

 

 

 

 

 

 

 

 

 

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

VIN, VOUT

-1.0 ~ 4.6

V

 

 

 

 

Voltage on VDD supply relative to Vss

VDD, VDDQ

-1.0 ~ 4.6

V

 

 

 

 

Storage temperature

TSTG

-55 ~ +150

°C

 

 

 

 

Power dissipation

PD

1

W

 

 

 

 

Short circuit current

IOS

50

mA

 

 

 

 

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Symbol

Min

Max

Unit

 

Clock

CCLK

2.5

4

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS, CAS, WE, CS, CKE, DQM

CIN

2.5

4.5

pF

 

 

 

 

 

 

 

Address

CADD

2.5

4.5

pF

 

 

 

 

 

 

 

DQ0 ~ DQ31

COUT

4.0

6.5

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

- 5 - REV. 1.1 Nov. '99

K4S643232C

 

 

 

 

 

CMOS SDRAM

 

DC OPERATING CONDITIONS

 

 

 

 

 

 

 

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

Min

Typ

 

Max

Unit

Note

 

Supply voltage

VDD, VDDQ

3.0

3.3

 

3.6

V

4

 

 

 

 

 

 

 

 

 

 

Input logic high voltage

VIH

2.0

3.0

 

VDDQ+0.3

V

1

 

 

 

 

 

 

 

 

 

 

Input logic low voltage

VIL

-0.3

0

 

0.8

V

2

 

 

 

 

 

 

 

 

 

 

Output logic high voltage

VOH

2.4

-

 

-

V

IOH = -2mA

 

 

 

 

 

 

 

 

 

 

Output logic low voltage

VOL

-

-

 

0.4

V

IOL = 2mA

 

 

 

 

 

 

 

 

 

 

Input leakage current

ILI

-10

-

 

10

uA

3

 

 

 

 

 

 

 

 

 

 

Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.

2.VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3.Any input 0V £ VIN £ VDDQ,

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4.The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter

Symbol

Test Condition

CAS

 

 

Version

 

 

Unit

Note

Latency

-55

-60

 

-70

 

-80

-10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating current

 

Burst length = 1

3

140

140

 

130

 

130

115

 

 

ICC1

tRC ³ tRC(min)

 

 

 

 

 

 

 

 

mA

2

(One bank active)

2

-

-

 

-

 

130

115

 

Io = 0 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Precharge standby current

ICC2P

CKE £ VIL(max), tCC = 15ns

 

 

 

2

 

 

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKE ³ VIH(min),

 

³ VIH(min), tCC = 15ns

 

 

 

 

 

 

 

 

 

 

ICC2N

CS

 

 

20

 

 

 

mA

 

Precharge standby current

Input signals are changed one time during 30ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in non power-down mode

ICC2NS

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

 

 

10

 

 

 

mA

 

 

 

 

 

 

 

 

 

 

Input signals are stable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Active standby current in

ICC3P

CKE £ VIL(max), tCC = 15ns

 

 

 

3

 

 

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

power-down mode

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKE ³ VIH(min),

 

³ VIH(min), tCC = 15ns

 

 

 

 

 

 

 

 

 

Active standby current in

ICC3N

CS

 

 

30

 

 

 

mA

 

Input signals are changed one time during 30ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

non power-down mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

 

 

 

 

 

 

 

 

 

(One bank active)

ICC3NS

 

 

20

 

 

 

mA

 

 

Input signals are stable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating current

 

Io = 0 mA

3

220

200

 

180

 

150

130

 

 

ICC4

Page burst

 

 

 

 

 

 

 

 

mA

2

(Burst mode)

2

-

-

 

-

 

130

110

 

2 Banks activated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Refresh current

ICC5

tRC ³ tRC(min)

3

200

200

 

180

 

160

150

mA

3

 

 

 

 

 

 

 

 

2

-

-

 

-

 

160

150

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Self refresh current

ICC6

CKE £ 0.2V

 

 

 

2

 

 

 

mA

4

 

 

 

 

 

 

 

 

 

 

 

 

 

450

 

 

 

uA

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2.Measured with outputs open.

3.Refresh period is 64ms.

4.K4S643232C-TC**

5.K4S643232C-TL**

- 6 -

REV. 1.1 Nov. '99

K4S643232C

 

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

 

 

 

 

 

 

 

 

 

Parameter

Value

 

 

Unit

AC input levels (Vih/Vil)

2.4/0.4

 

 

V

 

 

 

 

 

 

Input timing measurement reference level

1.4

 

 

V

 

 

 

 

 

 

Input rise and fall time

tr/tf = 1/1

 

 

ns

 

 

 

 

 

 

Output timing measurement reference level

1.4

 

 

V

 

 

 

 

 

 

Output load condition

See Fig. 2

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

Vtt = 1.4V

 

 

 

 

 

 

Output

870Ω

1200Ω

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

VOH (DC) = 2.4V, IOH = -2mA

Output

 

Z0 = 50Ω

 

 

 

 

 

 

 

VOL (DC) = 0.4V, IOL = 2mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50pF*1

 

 

 

 

 

 

 

 

 

 

 

 

50pF*1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

Note : 1. The DC/AC Test Output Load of K4S643232C-55/60/70 is 30pF. 2. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

 

 

Parameter

Symbol

 

 

 

 

 

 

Version

 

 

 

 

 

Unit

Note

 

 

-55

 

-60

 

-70

 

 

-80

-10

 

 

 

 

 

 

 

 

 

 

 

 

CAS Latency

CL

3

 

2

3

 

2

3

 

2

3

 

2

3

2

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK cycle time

tCC(min)

5.5

 

-

6

 

-

7

 

-

8

 

10

10

12

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row active to row active delay

tRRD(min)

 

 

 

 

 

 

2

 

 

 

 

 

 

CLK

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS to CAS delay

tRCD(min)

3

 

-

3

 

-

3

 

-

3

 

2

2

2

CLK

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row precharge time

tRP(min)

3

 

-

3

 

-

3

 

-

3

 

2

2

2

CLK

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row active time

tRAS(min)

7

 

-

7

 

-

7

 

-

6

 

5

5

4

CLK

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRAS(max)

 

 

 

 

 

 

100

 

 

 

 

 

 

us

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row cycle time

tRC(min)

10

 

-

10

 

-

10

 

-

9

 

7

7

6

CLK

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row cycle time in Auto refresh

tRFC(min)

12

 

-

12

 

-

10

 

-

9

 

7

7

6

CLK

1,6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Last data in to row precharge

tRDL(min)

 

 

 

 

 

 

2

 

 

 

 

 

 

CLK

2, 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Last data in to new col.address delay

tCDL(min)

 

 

 

 

 

 

1

 

 

 

 

 

 

CLK

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Last data in to burst stop

tBDL(min)

 

 

 

 

 

 

1

 

 

 

 

 

 

CLK

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Col. address to col. address delay

tCCD(min)

 

 

 

 

 

 

1

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode Register Set cycle time

tMRS(min)

 

 

 

 

 

 

2

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Number of valid output data

CAS Latency=3

 

 

 

 

 

 

2

 

 

 

 

 

 

ea

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAS Latency=2

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table.

- 7 -

REV. 1.1 Nov. '99

K4S643232C

 

 

 

 

 

CMOS SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

 

 

Version

 

 

Unit

 

 

 

-55

-60

-70

-80

-10

 

 

 

 

 

 

 

 

CLK cycle time

tCC(min)

5.5

6

7

8

10

ns

 

 

 

 

 

 

 

 

 

 

 

 

Row active to row active delay

tRRD(min)

11

12

14

16

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS to CAS delay

tRCD(min)

16.5

18

21

20

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

Row precharge time

tRP(min)

16.5

18

21

20

20

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

Row active time

tRAS(min)

38.5

42

49

48

48

ns

 

 

 

 

 

 

 

 

 

 

 

tRAS(max)

 

 

100

 

 

us

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row cycle time

tRC(min)

55

60

70

70

70

ns

 

 

 

 

 

 

 

 

 

 

 

 

Row cycle time in Auto refresh

tRFC(min)

66

72

70

70

70

ns

 

 

 

 

 

 

 

 

 

 

 

 

2.Minimum delay is required to complete write.

3.All parts allow every cycle column address change.

4.In case of row precharge interrupt, auto precharge and read burst stop.

5.For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency.

6.A new command should be issued after self refersh exit followed by tRFC.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

-55

-60

-70

-80

 

-10

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

 

Max

 

 

 

 

 

 

CLK cycle time

CAS Latency=3

tCC

5.5

1000

6

1000

7

1000

8

1000

10

 

1000

ns

1

 

 

 

 

 

 

 

CAS Latency=2

-

-

-

10

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK to valid

CAS Latency=3

tSAC

-

5

-

5.5

-

5.5

-

6

-

 

6

ns

1, 2

output delay

CAS Latency=2

-

-

-

-

-

-

-

6

-

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output data

 

tOH

2

-

2.5

-

2.5

-

2.5

-

2.5

 

-

ns

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK high pulse width

CAS Latency=3

tCH

2

-

2.5

-

3

-

3

-

3.5

 

-

ns

3

 

 

 

 

 

CAS Latency=2

-

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK low pulse width

CAS Latency=3

tCL

2

-

2.5

-

3

-

3

-

3.5

 

-

ns

3

 

 

 

 

 

CAS Latency=2

-

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input setup time

CAS Latency=3

tSS

1.5

-

1.5

-

1.75

-

2

-

2.5

 

-

ns

3

 

 

 

 

 

 

CAS Latency=2

-

-

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input hold time

 

tSH

1

-

1

-

1

-

1

-

1

 

-

ns

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK to output in Low-Z

 

tSLZ

1

-

1

-

1

-

1

-

1

 

-

ns

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK to output

CAS Latency=3

tSHZ

-

5

-

5.5

-

5.5

-

6

-

 

6

ns

 

in Hi-Z

CAS Latency=2

-

-

-

-

-

-

-

6

-

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note : 1. Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

- 8 -

REV. 1.1 Nov. '99

K4S643232C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,

 

 

CKEn-1

CKEn

 

CS

 

RAS

 

CAS

 

WE

DQM

BA0,1

A10/AP

 

Note

 

 

 

 

 

 

A9 ~ A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

Mode register set

H

X

 

L

 

L

 

L

 

L

X

 

OP code

 

1,2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto refresh

 

H

H

 

L

 

L

 

L

 

H

X

 

X

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

Refresh

 

 

 

Entry

L

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Self

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

H

 

H

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

refresh

 

Exit

L

H

 

 

 

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

X

 

X

 

X

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bank active & row addr.

 

H

X

 

L

 

L

 

H

 

H

X

V

Row address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read &

 

Auto precharge disable

H

X

 

L

 

H

 

L

 

H

X

V

L

 

Column

4

column address

 

 

 

 

 

 

 

 

 

 

address

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto precharge enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

(A0 ~ A7)

4,5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write &

 

Auto precharge disable

H

X

 

L

 

H

 

L

 

L

X

V

L

 

Column

4

column address

 

 

 

 

 

 

 

 

 

 

address

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto precharge enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

(A0 ~ A7)

4,5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Burst Stop

 

 

 

H

X

 

L

 

H

 

H

 

L

X

 

X

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Precharge

 

Bank selection

 

H

X

 

L

 

L

 

H

 

L

X

V

L

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All banks

 

 

 

 

 

X

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Entry

H

L

 

H

 

X

 

X

 

X

X

 

 

 

 

 

Clock suspend or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

L

 

V

 

V

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

active power down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Exit

L

H

 

X

 

X

 

X

 

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Entry

H

L

 

H

 

X

 

X

 

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Precharge power down mode

 

 

L

 

H

 

H

 

H

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Exit

L

H

 

H

 

X

 

X

 

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

V

 

V

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQM

 

 

 

H

 

 

 

 

 

X

 

 

 

 

 

 

V

 

X

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No operation command

 

H

X

 

H

 

X

 

X

 

X

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V=Valid, X=Dont care, H=Logic high, L=Logic low)

Notes :1. OP Code : Operand code

A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)

2.MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.

4.BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

- 9 -

REV. 1.1 Nov. '99

K4S643232C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

 

 

 

 

 

 

 

 

 

 

 

Register Programmed with MRS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

BA0 ~ BA1

A10/AP

 

A9

 

A8

 

A7

 

A6

 

A5

 

A4

A3

 

 

A2

 

A1

 

A0

Function

RFU

 

RFU

 

W.B.L

 

 

TM

 

 

 

CAS Latency

BT

 

 

 

Burst Length

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Mode

 

 

 

CAS Latency

 

Burst Type

 

 

 

 

Burst Length

 

 

A8

 

A7

 

 

Type

 

A6

A5

 

A4

Latency

 

A3

 

Type

A2

 

A1

A0

 

BT = 0

 

BT = 1

0

 

0

 

Mode Register Set

 

0

 

0

0

Reserved

0

Sequential

0

 

0

 

0

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

 

Reserved

 

0

 

0

1

Reserved

1

Interleave

0

 

0

 

1

2

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

 

Reserved

 

0

 

1

0

2

 

 

 

 

 

0

 

1

 

0

4

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

 

Reserved

 

0

 

1

1

3

 

 

 

 

 

0

 

1

 

1

8

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Burst Length

 

1

 

0

0

Reserved

 

 

 

 

1

 

0

 

0

Reserved

Reserved

A9

 

 

 

Length

 

1

 

0

1

Reserved

 

 

 

 

1

 

0

 

1

Reserved

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

Burst

 

1

 

1

0

Reserved

 

 

 

 

1

 

1

 

0

Reserved

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

Single Bit

 

1

 

1

1

Reserved

 

 

 

 

1

 

1

 

1

Full Page

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Full Page Length : x32 (256)

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1.Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.

- 10

REV. 1.1 Nov. '99

K4S643232C

 

 

 

 

 

 

 

CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Initial Address

 

Sequential

 

 

 

 

Interleave

 

A1

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

1

 

2

3

0

1

 

2

3

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

2

 

3

0

1

0

 

3

2

 

 

 

 

 

 

 

 

 

 

 

 

1

0

2

3

 

0

1

2

3

 

0

1

 

 

 

 

 

 

 

 

 

 

 

 

1

1

3

0

 

1

2

3

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

BURST SEQUENCE (BURST LENGTH = 8)

 

Initial Address

 

 

 

 

Sequential

 

 

 

 

 

 

Interleave

 

 

 

A2

 

A1

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

1

1

2

3

4

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6

7

0

1

0

3

2

5

4

7

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

2

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7

0

1

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3

0

1

6

7

4

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

1

3

4

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7

0

1

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2

1

0

7

6

5

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

4

5

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7

0

1

2

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5

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7

0

1

2

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

1

5

6

7

0

1

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5

4

7

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1

0

3

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

6

7

0

1

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0

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

7

0

1

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- 11

REV. 1.1 Nov. '99

K4S643232C

CMOS SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are thesame as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.

BANK ADDRESSES (BA0 ~ BA1)

This SDRAM is organized as four independent banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations.

ADDRESS INPUTS (A0 ~ A10)

The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10). The 11 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS,

CAS, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1.Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for both banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode reg-

ister.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

- 12

REV. 1.1 Nov. '99

K4S643232C

CMOS SDRAM

DEVICE OPERATIONS (Continued)

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,

RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) use A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP and BA0 ~ BA1. The write burst length is programmed using A9. A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification.

BURST READ

The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.

- 13

REV. 1.1 Nov. '99

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