Samsung K4S641632H-TC60, K4S641632H-TL75, K4S641632H-TL70, K4S641632H-TC75, K4S640832H-TL75 Datasheet
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SDRAM 64Mb H-die (x4, x8, x16) |
CMOS SDRAM |
64Mb H-die SDRAM Specification
Revision 1.4
November 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16) |
CMOS SDRAM |
Revision History
Revision 0.0 (May, 2003)
• Target spec release
Revision 0.1 (July, 2003)
• Preliminary spec release
Revision 0.2 (August, 2003)
• Modified IBIS characteristic.
Revision 1.0 (September, 2003)
• Finalized
Revision 1.1 (September, 2003)
• Corrected IBIS Specification.
Revision 1.2 (October, 2003)
• Deleted speed 7C at x4/x8.
Revision 1.3 (October, 2003)
• Deleted AC parameter notes 5.
Revision 1.4 (November, 2003)
• Modified Pin Function description.
Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16) |
CMOS SDRAM |
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
•JEDEC standard 3.3V power supply
•LVTTL compatible with multiplexed address
•Four banks operation
•MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
•All inputs are sampled at the positive going edge of the system clock
•Burst read single-bit write operation
•DQM (x4,x8) & L(U)DQM (x16) for masking
•Auto & self refresh
•64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. |
Orgainization |
Max Freq. |
Interface |
Package |
K4S640432H-TC(L)75 |
16Mb x 4 |
133MHz(CL=3) |
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K4S640832H-TC(L)75 |
8Mb x 8 |
133MHz(CL=3) |
LVTTL |
54pin TSOP(II) |
K4S641632H-TC(L)60 |
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166MHz(CL=3) |
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K4S641632H-TC(L)70 |
4Mb x 16 |
143MHz(CL=3) |
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K4S641632H-TC(L)75 |
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133MHz(CL=3) |
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Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16) |
CMOS SDRAM |
Package Physical Dimension
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0~8°C |
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0.25 TYP |
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0.010 |
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#54 |
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#28 |
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11.76±0.20 |
0.463±0.008 |
10.16 |
0.400 |
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0.45~0.75 0.018~0.030 |
#1 |
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#27 |
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0.125+0-0..075035 |
) |
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0.50 0.020 |
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22.62 |
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0.005+0.003-0.001 |
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MAX |
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( |
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0.891 |
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22.22 ± 0.10 |
0.21 ± 0.05 |
1.00 ± 0.10 |
1.20 |
MAX |
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0.875 ± 0.004 |
0.008 ± 0.002 |
0.039 ± 0.004 |
0.047 |
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0.10 |
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0.004MAX |
0.71 ) |
+0.10 |
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0.05 |
MIN |
( |
0.30 -0.05 |
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0.80 |
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0.002 |
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0.028 |
0.012 +-0.0040.002 |
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0.0315 |
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54Pin TSOP(II) Package Dimension
Rev. 1.4 November 2003
SDRAM 64Mb H-die (x4, x8, x16) |
CMOS SDRAM |
FUNCTIONAL BLOCK DIAGRAM
Data Input Register
Bank Select
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Counter Refresh |
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Decoder Row |
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4M x 4 / 2M x 8 / 1M x 16 |
AMP Sense |
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Buffer Row |
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4M x 4 / 2M x 8 / 1M x 16 |
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CLK |
Address |
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4M x 4 / 2M x 8 / 1M x 16 |
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4M x 4 / 2M x 8 / 1M x 16 |
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ADD |
Register |
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LRAS |
LCBR |
Buffer .Col |
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Column Decoder |
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Latency & Burst Length |
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LCKE |
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Programming Register |
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LRAS |
LCBR |
LWE |
LCAS |
LWCBR |
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Timing Register |
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CLK |
CKE |
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CS |
RAS |
CAS |
WE |
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I/O |
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LWE |
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Control |
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LDQM |
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Output |
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DQi |
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Buffer |
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LDQM
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 November 2003
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