K4S643232E-TL70
Samsung K4S643232E-TL70, K4S643232E-TL60, K4S643232E-TL45, K4S643232E-TC70, K4S643232E-TC60 Datasheet
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K4S643232E CMOS SDRAM
2M x 32 SDRAM
512K x 32bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 1.3
October 2001
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.3 (Oct. 2001)
K4S643232E CMOS SDRAM
Revision History
Revision 1.3 (October 24, 2000)
• Removed CAS Latency 1 from the spec.
Revision 1.2 (August 7, 2000) - Target
• Added CAS Latency 1
Revision 1.1 (March 14, 2001)
• Added K4S643232E-55
Revision 1.0 (October 20, 2000)
• Removed Note 5 in page 9. tRDL is set to 2CLK in any case regardless of using AP or frequency
Revision 0.4 (August 24, 2000)
• Updated DC spec
Revision 0.3 (August 1, 2000)
• Changed the wording of tRDL related note for User’s clear understanding
Revision 0.2 (July 18, 2000) - Preliminary
• Removed K4S643232E-40/55/7C
• Changed tSH of K4S643232E-45 from 0.7ns to 1.0ns
Revision 0.0 (March 14, 2000) - Target Spec.
• Initial draft
- 2 -
Rev. 1.3 (Oct. 2001)
K4S643232E CMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
GENERAL DESCRIPTIONFEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle
The K4S643232E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Part NO. Max Freq. Interface Package
K4S643232E-TC/L45 222MHz
K4S643232E-TC/L50 200MHz
K4S643232E-TC/L55 183MHz
K4S643232E-TC/L60 166MHz
K4S643232E-TC/L70 143MHz
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Refresh Counter
Row Buffer
Address Register
CLK
ADD
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
Data Input Register
Row Decoder Col. Buffer
LCAS LWCBR
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWE
LDQM
Sense AMP
Output BufferI/O Control
DQi
Timing Register
CLK CKE CS RAS CAS WE DQM
- 3 -
Samsung Electronics reserves the right to
*
change products or specification without
notice.
Rev. 1.3 (Oct. 2001)
K4S643232E CMOS SDRAM
PIN CONFIGURATION (Top view)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
N.C
VDD
DQM0
WE
CAS
RAS
CS
N.C
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
N.C
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C
VSS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
N.C
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86Pin TSOP (II)
(400mil x 875mil)
(0.5 mm Pin pitch)
- 4 -
Rev. 1.3 (Oct. 2001)
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