Mitsubishi MH4V64AXJJ-6, MH4V644AXJJ-6, MH4V644AXJJ-6S, MH4V64AXJJ-5, MH4V64AXJJ-5S Datasheet
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Preliminary |
MITSUBISHI LSIs |
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MH4V64/644AXJJ-5,-6,-5S,-6S |
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Some of contents are subject |
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to change without notice. |
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
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DESCRIPTION
This is family of 4194304 - word by 64 - bit dynamic RAM module. This consists of four industry standard 4Mx16 dynamic RAMs in TSOP and one industry EEPROM in TSSOP.
The mounting of TSOP on a card edge dual in line package provides any application where high densities and large of quantities memory are required.
This is a socket-type memory module,suitable for easy interchange of addition of modules.
FEATURES
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RAS |
CAS |
Address |
OE |
Cycle |
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access |
access |
access |
access |
time |
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time |
time |
time |
time |
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(max.ns) |
(max.ns) |
(max.ns) |
(max.ns) |
(min.ns) |
MH4V64AXJJ-5,5S |
50 |
13 |
25 |
13 |
90 |
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MH4V64AXJJ-6,6S |
60 |
15 |
30 |
15 |
110 |
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MH4V644AXJJ-5,5S |
50 |
13 |
25 |
13 |
90 |
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MH4V644AXJJ-6,6S |
60 |
15 |
30 |
15 |
110 |
ADDRESS
Part No. |
Row Add. |
Col Add. |
Refresh |
Refresh |
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Cycle |
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MH4V64AXJJ |
A0~A12 |
A0~A8 |
/RAS only Ref,Normal R/W |
8192/64ms |
CBR Ref,Hidden Ref |
4096/64ms |
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MH4V644AXJJ |
A0~A11 |
A0~A9 |
/RAS only Ref,Normal R/W |
4096/64ms |
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CBR Ref,Hidden Ref |
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APPLICATION
Main memory unit for computer,Microcomputer memory,Refresh memory for CRT.
*:Applicable to self refresh version(MH4V64/644AXJJ-5S,-6S) only
single 3.3V± 0.3V supply
Low stand-by power dissipation
7.2mW- - - - - - - - - LVCMOS input level 
operating power dissipation
MH4V64AXJJ-5,5S - - - - - 1584 mW(max.) MH4V64AXJJ-6,6S - - - - - 1440mW(max.) MH4V644AXJJ-5,5S - - - - 2016 mW(max.) MH4V644AXJJ-6,6S - - - - 1872 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output LVTTL compatible and low capacitance
Utilizes industry standard 4Mx16 RAMs in TSOP and industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx4)
Fast page mode , Read-modify-write,
CAS before RAS refresh,Hidden refresh capabilities. 
Early-write mode,OE to control output buffer
impedance.
MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
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ELECTRIC |
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( 1 / 25 )
Preliminary |
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MITSUBISHI LSIs |
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MH4V64/644AXJJ-5,-6,-5S,-6S |
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Some of contents are subject |
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to change without notice. |
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
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PIN CONFIGURATION |
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PIN |
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Front side |
PIN |
Back side |
PIN |
Front side |
PIN |
Back side |
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Number |
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Pin Name |
Number |
Pin Name |
Number |
Pin Name |
Number |
Pin Name |
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1 |
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Vss |
2 |
Vss |
73 |
/OE |
74 |
RFU |
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3 |
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DQ0 |
4 |
DQ32 |
75 |
Vss |
76 |
Vss |
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5 |
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DQ1 |
6 |
DQ33 |
77 |
Reserved |
78 |
Reserved |
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7 |
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DQ2 |
8 |
DQ34 |
79 |
Reserved |
80 |
Reserved |
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9 |
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DQ3 |
10 |
DQ35 |
81 |
Vcc |
82 |
Vcc |
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11 |
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Vcc |
12 |
Vcc |
83 |
DQ16 |
84 |
DQ48 |
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13 |
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DQ4 |
14 |
DQ36 |
85 |
DQ17 |
86 |
DQ49 |
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15 |
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DQ5 |
16 |
DQ37 |
87 |
DQ18 |
88 |
DQ50 |
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17 |
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DQ6 |
18 |
DQ38 |
89 |
DQ19 |
90 |
DQ51 |
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19 |
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DQ7 |
20 |
DQ39 |
91 |
Vss |
92 |
Vss |
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21 |
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Vss |
22 |
Vss |
93 |
DQ20 |
94 |
DQ52 |
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23 |
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/CAS0 |
24 |
/CAS4 |
95 |
DQ21 |
96 |
DQ53 |
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25 |
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/CAS1 |
26 |
/CAS5 |
97 |
DQ22 |
98 |
DQ54 |
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27 |
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Vcc |
28 |
Vcc |
99 |
DQ23 |
100 |
DQ55 |
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29 |
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A0 |
30 |
A3 |
101 |
Vcc |
102 |
Vcc |
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31 |
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A1 |
32 |
A4 |
103 |
A6 |
104 |
A7 |
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33 |
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A2 |
34 |
A5 |
105 |
A8 |
106 |
A11 |
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35 |
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Vss |
36 |
Vss |
107 |
Vss |
108 |
Vss |
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37 |
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DQ8 |
38 |
DQ40 |
109 |
A9 |
110 |
A12/NC(note) |
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39 |
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DQ9 |
40 |
DQ41 |
111 |
A10 |
112 |
NC |
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41 |
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DQ10 |
42 |
DQ42 |
113 |
Vcc |
114 |
Vcc |
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43 |
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DQ11 |
44 |
DQ43 |
115 |
/CAS2 |
116 |
/CAS6 |
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45 |
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Vcc |
46 |
Vcc |
117 |
/CAS3 |
118 |
/CAS7 |
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47 |
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DQ12 |
48 |
DQ44 |
119 |
Vss |
120 |
Vss |
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49 |
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DQ13 |
50 |
DQ45 |
121 |
DQ24 |
122 |
DQ56 |
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51 |
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DQ14 |
52 |
DQ46 |
123 |
DQ25 |
124 |
DQ57 |
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53 |
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DQ15 |
54 |
DQ47 |
125 |
DQ26 |
126 |
DQ58 |
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55 |
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Vss |
56 |
Vss |
127 |
DQ27 |
128 |
DQ59 |
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57 |
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Reserved |
58 |
Reserved |
129 |
Vcc |
130 |
Vcc |
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59 |
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Reserved |
60 |
Reserved |
131 |
DQ28 |
132 |
DQ60 |
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61 |
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RFU |
62 |
FRU |
133 |
DQ29 |
134 |
DQ61 |
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63 |
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Vcc |
64 |
Vcc |
135 |
DQ30 |
136 |
DQ62 |
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65 |
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RFU |
66 |
RFU |
137 |
DQ31 |
138 |
DQ63 |
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67 |
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/WE |
68 |
RFU |
139 |
Vss |
140 |
Vss |
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69 |
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/RAS0 |
70 |
RFU |
141 |
SDA |
142 |
SCL |
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71 |
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NC |
72 |
RFU |
143 |
Vcc |
144 |
Vcc |
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RFU:Reserved Future Use |
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NC,RFU,Reserved: NO CONNECTION |
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Note:A12 ... MH4V64AXJJ , NC ... MH4V644AXJJ |
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MIT-DS-0072-0.5 |
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MITSUBISHI |
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26/Feb./1997 |
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ELECTRIC |
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( 2 / 25 )
Preliminary |
MITSUBISHI LSIs |
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MH4V64/644AXJJ-5,-6,-5S,-6S |
|||
Some of contents are subject |
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to change without notice. |
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
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Block Diagram
Address /OE /WE /RAS0 /CAS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/CAS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CAS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CAS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/UCAS D0
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/UCAS D1
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
/CAS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/CAS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/CAS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/CAS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/UCAS D2
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
/LCAS /RAS /WE /OE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/UCAS D3
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
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SERIAL PD |
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Vcc |
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D0 |
to D3 |
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SDA |
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Vss |
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C1~C4 |
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SCL |
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A0 A1 |
A2 |
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D0 |
to D3 |
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Vss |
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MIT-DS-0072-0.5 |
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MITSUBISHI |
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26/Feb./1997 |
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ELECTRIC |
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( 3 / 25 )
Preliminary |
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MITSUBISHI LSIs |
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MH4V64/644AXJJ-5,-6,-5S,-6S |
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Some of contents are subject |
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to change without notice. |
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FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
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Serial Presence Detece TABLE (MH4V64AXJJ-5,-6) |
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Bytes |
Function described |
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SPD entry data |
SPD DATA entry(Hex) |
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1 |
Total # bytes of SPD memory device |
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256 Bytes |
08 |
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2 |
Fundamental memory type |
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FPM DRAM |
01 |
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3 |
# Row Addresses on this assembly |
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A0-A12 |
0D |
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4 |
# Column Addresses on this assembly |
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A0-A8 |
09 |
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5 |
# Module Banks on this assembly |
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1bank |
01 |
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6 |
Data Width of this assembly... |
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x64 |
40 |
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7 |
... Data Width continuation |
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0 |
00 |
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8 |
Voltage interface standard of this assembly |
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3.3V LVTTL |
02 |
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9 |
RAS# access time of this assembly |
-5 |
50ns |
32 |
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-6 |
60ns |
3C |
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10 |
CAS# access time of this assembly |
-5 |
13ns |
0D |
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-6 |
15ns |
0F |
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11 |
DIMM Configuration type (Non-parity,Parity,ECC) |
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non parity |
00 |
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12 |
Refresh Rate/Type |
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N/R(15.625uS) |
00 |
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13 |
DRAM width,Primary DRAM |
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x16 |
10 |
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14 |
Error Checking DRAM data width |
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N/A |
00 |
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15-31 |
Reserved for future offerings |
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open |
00 |
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32-61 |
Superset Memory type(may be used in future) |
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open |
00 |
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62 |
SPD Data Revision Code |
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Rev 1 |
01 |
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63 |
Checksum for bytes 0-62 |
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Check sum for -5 |
32 |
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Check sum for -6 |
3E |
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64-71 |
Manufacturers JEDEC ID code per JEP-106 |
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MITSUBISHI |
1CFFFFFFFFFFFFFF |
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72 |
Manufacturing location |
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Miyoshi,Japan |
01 |
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Tajima,Japan |
02 |
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NC,USA |
03 |
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Germany |
04 |
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73-90 |
Manufacturer's Part Number |
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MH4V64AXJJ-5 |
4D483456363441584A4A2D352D35202020202020 |
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MH4V64AXJJ-6 |
4D483456363441584A4A2D362D36202020202020 |
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91-92 |
Revision Code |
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PCB revision |
rrrr |
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93-94 |
Manufacturing date |
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year/week code |
yy/ww |
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95-98 |
Assembly Serial Number |
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serial number |
ssssssss |
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99-125 |
Manufacturer Specific Data |
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open |
00 |
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126-127 |
Reserved |
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open |
00 |
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128-255 |
Open User Free-Form area not defined |
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open |
00 |
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MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
|
ELECTRIC |
|
( 4 / 25 )
Preliminary |
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|
|
MITSUBISHI LSIs |
|||||
MH4V64/644AXJJ-5,-6,-5S,-6S |
||||||||||
Some of contents are subject |
||||||||||
to change without notice. |
|
|
|
|
|
|
|
|||
|
|
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
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Serial Presence Detece TABLE (MH4V64AXJJ-5S,-6S) |
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Bytes |
Function described |
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SPD entry data |
SPD DATA entry(Hex) |
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1 |
Total # bytes of SPD memory device |
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256 Bytes |
08 |
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2 |
Fundamental memory type |
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FPM DRAM |
01 |
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3 |
# Row Addresses on this assembly |
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A0-A12 |
0D |
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4 |
# Column Addresses on this assembly |
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A0-A8 |
09 |
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5 |
# Module Banks on this assembly |
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1bank |
01 |
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6 |
Data Width of this assembly... |
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x64 |
40 |
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7 |
... Data Width continuation |
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0 |
00 |
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8 |
Voltage interface standard of this assembly |
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3.3V LVTTL |
02 |
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9 |
RAS# access time of this assembly |
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-5S |
50ns |
32 |
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-6S |
60ns |
3C |
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10 |
CAS# access time of this assembly |
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-5S |
13ns |
0D |
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-6S |
15ns |
0F |
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11 |
DIMM Configuration type (Non-parity,Parity,ECC) |
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non parity |
00 |
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12 |
Refresh Rate/Type |
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S/R(15.625uS) |
80 |
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13 |
DRAM width,Primary DRAM |
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x16 |
10 |
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14 |
Error Checking DRAM data width |
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N/A |
00 |
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15-31 |
Reserved for future offerings |
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open |
00 |
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32-61 |
Superset Memory type(may be used in future) |
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open |
00 |
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62 |
SPD Data Revision Code |
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Rev 1 |
01 |
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63 |
Checksum for bytes 0-62 |
|
|
|
Check sum for -5 |
B2 |
|
||
|
|
|
|
|
|
Check sum for -6 |
BE |
|
||
|
64-71 |
Manufacturers JEDEC ID code per JEP-106 |
|
MITSUBISHI |
1CFFFFFFFFFFFFFF |
|
||||
|
72 |
Manufacturing location |
|
|
|
Miyoshi,Japan |
01 |
|
|
|
|
|
|
|
|
|
Tajima,Japan |
02 |
|
|
|
|
|
|
|
|
|
NC,USA |
03 |
|
|
|
|
|
|
|
|
|
Germany |
04 |
|
|
|
|
73-90 |
Manufacturer's Part Number |
|
|
|
MH4V64AXJJ-5S |
4D483456363441584A4A2D355335532020202020 |
|
||
|
|
|
|
|
|
MH4V64AXJJ-6S |
4D483456363441584A4A2D365336532020202020 |
|
||
|
91-92 |
Revision Code |
|
|
|
PCB revision |
rrrr |
|
||
|
93-94 |
Manufacturing date |
|
|
|
year/week code |
yy/ww |
|
||
|
95-98 |
Assembly Serial Number |
|
|
|
serial number |
ssssssss |
|
||
|
99-125 |
Manufacturer Specific Data |
|
|
|
open |
00 |
|
|
|
|
126-127 |
Reserved |
|
|
|
open |
00 |
|
|
|
|
128-255 |
Open User Free-Form area not defined |
|
open |
00 |
|
|
|||
MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
|
ELECTRIC |
|
( 5 / 25 )
Preliminary |
|
|
|
MITSUBISHI LSIs |
|||||
MH4V64/644AXJJ-5,-6,-5S,-6S |
|||||||||
Some of contents are subject |
|||||||||
to change without notice. |
|
|
|
|
|
|
|||
|
|
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
|||||||
|
|
|
|
|
|
|
|||
|
Serial Presence Detece TABLE (MH4V644AXJJ-5,-6) |
|
|
|
|||||
|
|
|
|
|
|
|
|
||
|
Bytes |
Function described |
|
|
SPD entry data |
SPD DATA entry(Hex) |
|
||
0 |
Defines # bytes written into serial memory at module mfgr |
128 |
80 |
|
|
||||
1 |
Total # bytes of SPD memory device |
|
256 Bytes |
08 |
|
|
|||
2 |
Fundamental memory type |
|
|
FPM DRAM |
01 |
|
|
||
3 |
# Row Addresses on this assembly |
|
A0-A11 |
0C |
|
||||
4 |
# Column Addresses on this assembly |
|
A0-A9 |
0A |
|
||||
5 |
# Module Banks on this assembly |
|
1bank |
01 |
|
|
|||
6 |
Data Width of this assembly... |
|
x64 |
40 |
|
|
|||
7 |
... Data Width continuation |
|
|
0 |
00 |
|
|
||
8 |
Voltage interface standard of this assembly |
|
3.3V LVTTL |
02 |
|
|
|||
9 |
RAS# access time of this assembly |
-5 |
50ns |
32 |
|
|
|||
|
|
|
|
-6 |
60ns |
3C |
|
||
10 |
CAS# access time of this assembly |
-5 |
13ns |
0D |
|
||||
|
|
|
|
-6 |
15ns |
0F |
|
||
11 |
DIMM Configuration type (Non-parity,Parity,ECC) |
|
non parity |
00 |
|
|
|||
12 |
Refresh Rate/Type |
|
|
N/R(15.625uS) |
00 |
|
|
||
13 |
DRAM width,Primary DRAM |
|
|
x16 |
10 |
|
|
||
14 |
Error Checking DRAM data width |
|
N/A |
00 |
|
|
|||
15-31 |
Reserved for future offerings |
|
|
open |
00 |
|
|
||
32-61 |
Superset Memory type(may be used in future) |
|
open |
00 |
|
|
|||
62 |
SPD Data Revision Code |
|
|
Rev 1 |
01 |
|
|
||
63 |
Checksum for bytes 0-62 |
|
|
Check sum for -5 |
32 |
|
|
||
|
|
|
|
|
Check sum for -6 |
3E |
|
||
64-71 |
Manufacturers JEDEC ID code per JEP-106 |
|
MITSUBISHI |
1CFFFFFFFFFFFFFF |
|
||||
72 |
Manufacturing location |
|
|
Miyoshi,Japan |
01 |
|
|
||
|
|
|
|
|
Tajima,Japan |
02 |
|
|
|
|
|
|
|
|
NC,USA |
03 |
|
|
|
|
|
|
|
|
Germany |
04 |
|
|
|
73-90 |
Manufacturer's Part Number |
|
MH4V644AXJJ-5 |
4D48345636343441584A4A2D352D352020202020 |
|
||||
|
|
|
|
|
MH4V644AXJJ-6 |
4D48345636343441584A4A2D362D362020202020 |
|
||
91-92 |
Revision Code |
|
|
PCB revision |
rrrr |
|
|||
93-94 |
Manufacturing date |
|
|
year/week code |
yy/ww |
|
|||
95-98 |
Assembly Serial Number |
|
|
serial number |
ssssssss |
|
|||
99-125 |
Manufacturer Specific Data |
|
|
open |
00 |
|
|
||
126-127 |
Reserved |
|
|
open |
00 |
|
|
||
128-255 |
Open User Free-Form area not defined |
|
open |
00 |
|
|
|||
MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
|
ELECTRIC |
|
( 6 / 25 )
Preliminary |
|
|
|
MITSUBISHI LSIs |
||||
MH4V64/644AXJJ-5,-6,-5S,-6S |
||||||||
Some of contents are subject |
||||||||
to change without notice. |
|
|
|
|
|
|
||
|
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
|||||||
|
|
|
|
|
|
|
||
Serial Presence Detece TABLE (MH4V644AXJJ-5S,-6S) |
|
|
|
|||||
|
|
|
|
|
|
|
||
Bytes |
Function described |
|
|
SPD entry data |
SPD DATA entry(Hex) |
|
||
0 |
Defines # bytes written into serial memory at module mfgr |
128 |
80 |
|
|
|||
1 |
Total # bytes of SPD memory device |
|
256 Bytes |
08 |
|
|
||
2 |
Fundamental memory type |
|
|
FPM DRAM |
01 |
|
|
|
3 |
# Row Addresses on this assembly |
|
A0-A11 |
0C |
|
|||
4 |
# Column Addresses on this assembly |
|
A0-A9 |
0A |
|
|||
5 |
# Module Banks on this assembly |
|
1bank |
01 |
|
|
||
6 |
Data Width of this assembly... |
|
x64 |
40 |
|
|
||
7 |
... Data Width continuation |
|
0 |
00 |
|
|
||
8 |
Voltage interface standard of this assembly |
|
3.3V LVTTL |
02 |
|
|
||
9 |
RAS# access time of this assembly |
-5S |
50ns |
32 |
|
|
||
|
|
|
-6S |
60ns |
3C |
|
||
10 |
CAS# access time of this assembly |
-5S |
13ns |
0D |
|
|||
|
|
|
-6S |
15ns |
0F |
|
||
11 |
DIMM Configuration type (Non-parity,Parity,ECC) |
|
non parity |
00 |
|
|
||
12 |
Refresh Rate/Type |
|
|
S/R(15.625uS) |
80 |
|
|
|
13 |
DRAM width,Primary DRAM |
|
x16 |
10 |
|
|
||
14 |
Error Checking DRAM data width |
|
N/A |
00 |
|
|
||
15-31 |
Reserved for future offerings |
|
open |
00 |
|
|
||
32-61 |
Superset Memory type(may be used in future) |
|
open |
00 |
|
|
||
62 |
SPD Data Revision Code |
|
|
Rev 1 |
01 |
|
|
|
63 |
Checksum for bytes 0-62 |
|
|
Check sum for -5S |
B2 |
|
||
|
|
|
|
Check sum for -6S |
BE |
|
||
64-71 |
Manufacturers JEDEC ID code per JEP-106 |
|
MITSUBISHI |
1CFFFFFFFFFFFFFF |
|
|||
72 |
Manufacturing location |
|
|
Miyoshi,Japan |
01 |
|
|
|
|
|
|
|
Tajima,Japan |
02 |
|
|
|
|
|
|
|
NC,USA |
03 |
|
|
|
|
|
|
|
Germany |
04 |
|
|
|
73-90 |
Manufacturer's Part Number |
|
MH4V644AXJJ-5S |
4D48345636343441584A4A2D3553355320202020 |
|
|||
|
|
|
|
MH4V644AXJJ-6S |
4D48345636343441584A4A2D3653365320202020 |
|
||
91-92 |
Revision Code |
|
|
PCB revision |
rrrr |
|
||
93-94 |
Manufacturing date |
|
|
year/week code |
yy/ww |
|
||
95-98 |
Assembly Serial Number |
|
|
serial number |
ssssssss |
|
||
99-125 |
Manufacturer Specific Data |
|
open |
00 |
|
|
||
126-127 |
Reserved |
|
|
open |
00 |
|
|
|
128-255 |
Open User Free-Form area not defined |
|
open |
00 |
|
|
||
MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
|
ELECTRIC |
|
( 7 / 25 )
Preliminary |
MITSUBISHI LSIs |
||
MH4V64/644AXJJ-5,-6,-5S,-6S |
|||
Some of contents are subject |
|||
to change without notice. |
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM |
||
|
|||
|
|
|
|
FUNCTION
The MH4V64/644AXJJ provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., Fast page mode, /RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
|
Operation |
|
|
Inputs |
|
|
Input/Output |
Refresh |
Remark |
|||
|
/RAS |
/CAS |
/W |
/OE |
Row |
Column |
Input |
Output |
||||
|
|
address |
address |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|||
Read |
ACT |
ACT |
NAC |
ACT |
APD |
APD |
OPN |
VLD |
YES |
Fast page |
||
|
|
|
|
|
|
|
|
|
|
|
||
Write (Early write) |
ACT |
ACT |
ACT |
DNC |
APD |
APD |
VLD |
OPN |
YES |
|||
mode |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||
Write (Delayed write) |
ACT |
ACT |
ACT |
DNC |
APD |
APD |
VLD |
IVD |
YES |
|||
identical |
||||||||||||
Read-modify-write |
ACT |
ACT |
ACT |
ACT |
APD |
APD |
VLD |
VLD |
YES |
|||
|
||||||||||||
/RAS-only refresh |
ACT |
NAC |
DNC |
DNC |
APD |
DNC |
DNC |
OPN |
YES |
|
||
Hidden refresh |
ACT |
ACT |
NAC |
ACT |
APD |
DNC |
OPN |
VLD |
YES |
|
||
/CAS before /RAS refresh |
ACT |
ACT |
NAC |
DNC |
DNC |
DNC |
DNC |
OPN |
YES |
|
||
Standby |
NAC |
DNC |
DNC |
DNC |
DNC |
DNC |
DNC |
OPN |
NO |
|
||
Self refresh * |
ACT |
ACT |
NAC |
DNC |
DNC |
DNC |
DNC |
OPN |
YES |
|
||
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
*MH4V64/644AXJJ-5S,-6S only
MIT-DS-0072-0.5 |
MITSUBISHI |
26/Feb./1997 |
|
ELECTRIC |
|
( 8 / 25 )
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