νAccess Times of 70, 85, 100ns
νAvailable with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130)
ν2V Data Retention (LP Versions)
νCS and OE Functions for Bus Control
νTTL Compatible Inputs and Outputs
νFully Static, No Clocks
νOrganized as 128Kx8
νIndustrial, Military and Commercial Temperature Ranges
νThru-hole and Surface Mount Packages JEDEC Pinout
•32 pin Ceramic DIP, 0.6 mils wide (Package 9)
•32 lead Ceramic SOJ (Package 140)
νSingle +5V (±10%) Supply Operation
The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1 |
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32 DIP |
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I/O0-7 |
DataInputs/Outputs |
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32 SOJ |
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A0-16 |
Address Inputs |
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WE |
Write Enable |
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CS1, CS2 |
Chip Selects |
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NC |
1 |
32 |
VCC |
OE |
Output Enable |
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A16 |
2 |
31 |
A15 |
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A14 |
3 |
30 |
NC/CS2* |
VCC |
Power (+5V ±10%) |
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A12 |
4 |
29 |
WE |
VSS |
Ground |
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A7 |
5 |
28 |
A13 |
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A6 |
6 |
27 |
A8 |
NC |
Not Connected |
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A5 |
7 |
26 |
A9 |
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A4 |
8 |
25 |
A11 |
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A3 |
9 |
24 |
OE |
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A2 |
10 |
23 |
A10 |
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A1 |
11 |
22 |
CS1 |
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AØ |
12 |
21 |
I/O7 |
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I/OØ |
13 |
20 |
I/O6 |
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I/O1 |
14 |
19 |
I/O5 |
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I/O2 |
15 |
18 |
I/O4 |
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VSS |
16 |
17 |
I/O3 |
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* Pin 30 is NC for 88128 or CS2 for 88130.
March 2002 Rev. 16 |
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com |
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Voltage on any pin relative to Vss |
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-0.5 to 7.0 |
V |
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! |
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Commercial |
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0 to +70 |
°C |
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Industrial |
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-40 to +85 |
°C |
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Military |
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-55 to +125 |
°C |
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Storage Temperature, Plastic |
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-65 to +150 |
°C |
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Power Dissipation |
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1 |
W |
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OutputCurrent |
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20 |
mA |
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Junction Temperature, TJ |
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175 |
°C |
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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# $% |
$'$ |
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AddressLines |
CI |
VIN = Vcc or Vss, f = 1.0MHz |
12 |
pF |
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Input/OutputLines |
CO |
VOUT = Vcc or Vss, f = 1.0MHz |
14 |
pF |
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These parameters are sampled, not 100% tested.
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$' |
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$) |
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X |
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H |
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X |
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X |
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Standby |
High Z |
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Icc2, Icc3 |
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X |
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X |
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L |
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X |
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Standby |
High Z |
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Icc2, Icc3 |
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X |
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X |
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L |
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X |
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Output Deselect |
High Z |
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Icc1 |
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H |
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L |
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H |
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H |
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Output Deselect |
High Z |
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Icc1 |
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L |
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L |
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H |
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H |
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Read |
Data Out |
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Icc1 |
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X |
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L |
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H |
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L |
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Write |
Data In |
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Icc1 |
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" " " |
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# |
$% |
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& |
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Supply Voltage |
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VCC |
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4.5 |
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5.0 |
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5.5 |
V |
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Supply Voltage |
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VSS |
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0 |
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0 |
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0 |
V |
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Input High Voltage |
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VIH |
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2.2 |
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— |
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Vcc +0.5 |
V |
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Input Low Voltage |
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VIL |
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-0.3 |
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— |
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+0.8 |
V |
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$'$* |
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* |
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# |
& |
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Input Leakage Current |
ILI |
VIN = 0V to VCC |
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-5 |
— |
+5 |
µA |
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Output Leakage Current |
ILO |
VI/O = 0V to VCC, |
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1 ³ VIH and/or |
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-10 |
— |
+10 |
µA |
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CS |
CS2 £ VIL |
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1 = VIL, II/O = 0mA, Min Cycle |
(70-85ns) |
— |
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120 |
mA |
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Operating Power Supply Current |
ICC1 |
WE, |
CS |
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(100ns) |
— |
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110 |
mA |
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CS2 = VIH |
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Standby (TTL) Power Supply Current |
ICC2 |
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1 ³ VIH and/or |
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2 £ VIL, VIN ³ VIH or £ VIL |
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— |
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10 |
mA |
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CS |
CS |
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1 ³ VCC -0.2V and/or |
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2 £ Vcc +0.2V |
C |
— |
1 |
5 |
mA |
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CS |
CS |
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Full Standby Power Supply Current |
ICC3 |
VIN ³ Vcc -0.2V or VIN £ 0.2V |
LP |
— |
— |
1 |
mA |
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OutputLowVoltage |
VOL |
IOL = 2.1mA |
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— |
— |
0.4 |
V |
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Output High Voltage |
VOH |
IOH = -1.0mA |
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2.4 |
— |
— |
V |
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NOTE: DC test conditions : VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 |
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( " +
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# $% |
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,-* |
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./ * |
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0--* |
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1 " |
% 2 |
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& |
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& |
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& |
* |
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Read Cycle Time |
tAVAV |
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tRC |
70 |
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85 |
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100 |
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ns |
AddressAccessTime |
tAVQV |
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tAA |
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70 |
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85 |
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100 |
ns |
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ChipSelectAccessTime |
tELQV |
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tACS |
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70 |
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85 |
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100 |
ns |
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tSHQV |
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tACS |
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70 |
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85 |
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100 |
ns |
ChipSelecttoOutput inLowZ (1) |
tELQX |
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tCLZ |
3 |
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3 |
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3 |
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ns |
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tSHQX |
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tCLZ |
3 |
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3 |
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3 |
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ns |
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ChipDisabletoOutputinHighZ (1) |
tEHQZ |
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tCHZ |
0 |
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30 |
0 |
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30 |
0 |
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30 |
ns |
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tSLQZ |
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tCHZ |
0 |
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30 |
0 |
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30 |
0 |
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30 |
ns |
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OutputHoldfromAddressChange |
tAVQX |
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tOH |
3 |
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3 |
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3 |
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ns |
OutputEnabletoOutputValid |
tGLQV |
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tOE |
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25 |
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30 |
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50 |
ns |
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OutputEnabletoOutputinLowZ(1) |
tGLQX |
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tOLZ |
0 |
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0 |
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0 |
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ns |
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OutputDisabletoOutputinHighZ(1) |
tGHQZ |
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tOHZ |
0 |
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30 |
0 |
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30 |
0 |
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30 |
ns |
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1. This parameter is guaranteed by design but not tested.
" |
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Figure 1 |
Vcc |
Figure 2 |
Vcc |
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480Ω |
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480Ω |
Q |
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Q |
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255Ω |
30pF |
255Ω |
5pF |
Input Pulse Levels |
VSS to 3.0V |
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Input Rise and Fall Times |
5ns |
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Input and Output Timing Levels |
1.5V |
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OutputLoad |
Figure 1 |
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NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com