Samsung KT8557BN, KT8557BJ, KT8554BN, KT8554BJ, KT8554BD Datasheet

KT8554B/7B	1 CHIP CODECS

INTRODUCTION

16-CERDIP

The KT8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM)

system.

These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filter-

ing functions in PCM system. They are intended to be used 16-DIP- at the analog termination of a PCM line or trunk.

These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information.

FEATURES		16-SOP-BD300
∙	Complete CODEC and filtering system	-SG

∙Meets or exceeds AT&T D3/D4 and CCITT specifications

μ-Law : KT8554B, A-Law : KT8557B

∙On-chip auto zero, sample and hold, and precision voltage references

∙ Low power dissipation : 60mW (operating) 3mW (standby)

∙± 5V operation

∙TTL or CMOS compatible

∙ Automatic power down	ORDERING INFORMATION
	Device	Package		Operating Temperature
	KT8554BJ	16-CERDIP		- 25 ~ 125°C
	KT8557BJ
	KT8557BN	16-DIP-300A		- 25 ~ 70°C
	KT8554BN
PIN CONFIGURATION	KT8554BD	16-SOP-BD300		- 25 ~ 70°C
	KT8557BD	-SG

V	BB	1	16	VF	X	I+
GNDA		2	15	VF	X	I-
VF RO		3	14	GS X
VCC		4	13	TS X
			KT8554B/7B
FS R		5	12	FS XS
DR		6	11	D X
BCLK R/CLKSEL		7	10	BCLK X
MCLK R/PDN		8	9	MCLK X

Fig. 1

KT8554B/7B	1 CHIP CODECS

PIN DESCRIPTION

Pin No

Symbol

Description

1

VBB

VBB = - 5V ±5%.

2

GNDA

Analog ground.

3

VFRO

Analog output of the receive power Amp.

4

VCC

VCC = +5V ± 5%.

5

FSR

Receive frame sync pulse. 8KHz pulse train.

6

DR

PCM data input.

BCLKR /

Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master

7

clock in normal operation and BCLKX is used for both TX and RX directions.

CLKSEL

Alternately direct clock input available, very from 64KHz to 2.048MHz.

MCLKR /

When MCLKR is connected continuously high, the device is powered down.

8

Normally connected continusously low, MCLKX is selected for all DAC timing.

PDN

Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.

9

MCLKX

Must be1.536MHz/1.544MHz or 2.048MHz.

10

BCLKX

May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLKX

in normal operation.

11

DX

PCM data output.

12

FSX

TX frame sync pulse. 8KHz pulse train.

13

Changed from high to low during the encoder timeslot. Open drain output.

TS

X

14

GSX

Analog output of the TX input amplifier.

Used to set gain through external resistor.

15

VFXI -

Inverting input stage of the TX analog signal.

16

VFXI +

Non-inverting input stage of the TX analog signal.

ABSOLUTE MAXIMUM RATINGS (Ta = 25oC)

Characteristic

Symbol

Value

Unit

Positive Supply Voltage

VCC

7

V

Negative Supply Voltage

VBB

- 7

V

Voltage at Any Analog Input or Output

VI (A)

VCC + 0.3 to VBB - 0.3

V

Voltage at Any Digital Input or Output

Vl (D)

VCC + 0.3 to GNDA - 0.3

V

Operating Temperature Range

Ta

- 25 to + 125

oC

Storage Temperature Range

TSTG

- 65 to + 150

oC

Lead Temperature (Soldering, 10 secs)

TLEAD

300

oC

KT8554B/7B	1 CHIP CODECS

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ±5%, VBB = - 5.0V ±5%, GNDA = 0V, Ta = 0 oC to 70 oC ; typical characteristics specified at VCC = 5.0V, VBB = - 5.0V, Ta = 25 oC ; all signals referenced to GNDA).

Characteristic		Symbol				Test Conditions	Min	Typ	Max	Unit
Power Dissipation
Power-Down Current		ICC (DOWN)		No Load				0.5	1.5	mA
Power-Down Current		IBB (DOWN)		No Load				0.05	0.3	mA
Active Current		ICC (A)		No Load				6.0	9.0	mA
Active Current		IBB (A)		No Load				6.0	9.0	mA
Digital Interface
Input Low Voltage		VIL							0.6	V
Input High Voltage		VIH					2.2			V
Input Low Current		IIL		GNDA ≤ VIN≤VIL, all digital inputs			-10		10	μA
Input High Current		IIH		VIH ≤ VIN ≤ VCC			-10		10	μA
				DX,IL = 3.2mA					0.4	V
Output Low Voltage		VOL		SIGR, IL = 1.0mA					0.4	V
					TS	X, IL = 3.2mA,open drain			0.4	V
Output High Voltage		VOH		DX, IH = -3.2mA			2.4			V
				SIGR, IH = -1.0 mA			2.4			V
Output Current in High Impedance		IO (HZ)		DX, GNDA ≤ VO ≤ VCC			-10		10	μA
State (TRI-STATE)
Analog Interface with Receive Filter
Output Resistance		RO		Pin VFRO				1	3	Ω
Load Resistance		RL		VFRO = ±2.5V			600			Ω
Load Capacitance		CL							500	pF
Output DC Offset Voltage		VOO (RX)					-200		200	mV
Analog Interface with Transmit input Amplifier
Input Leakage Current		ILKG		-2.5V≤V≤+2.5V, VFXI + or VFXI -			-200		200	nA
Input Resistance		RI		-2.5V≤V≤+2.5V, VFXI + or VFXI -			10			MΩ
Output Resistance		RO		Closed loop, unity gain				1	3	Ω
Load Resistance		RL		GSX			10			KΩ
Load Capacitance		CL		GSX					50	pF
Output Dynamic Range		VOD (TX)		GSX, RL≤10KW			±2.8			V
Voltage Gain		GV		VFXI + to GSX			5,000			V/V
Unity Gain Bandwidth		BW					1	2		MHz
Offset Voltage		VIO (TX)					-20		20	mV
Common-Mode Voltage		VCM (TX)		CMRRXA > 60dB			-2.5		2.5	V
Common-Mode Rejection Ratio		CMRR		DC Test			60			dB
Power Supply Rejection Ratio		PSRR		DC Test			60			dB