Philips NE570NB, NE570D, NE571N, NE571F, NE571D Datasheet
...
INTEGRATED CIRCUITS
SA571
Compandor
Product specification |
1997 Aug 14 |
IC17 Data Handbook
m n r
Philips Semiconductors |
Product specification |
|
|
|
|
|
|
|
Compandor |
SA571 |
|
|
|
|
|
|
|
DESCRIPTION
The SA571 is a versatile low cost dual gain control circuit in which either channel may be used as a dynamic range compressor or expandor. Each channel has a full-wave rectifier to detect the average value of the signal, a linerarized temperature-compensated variable gain cell, and an operational amplifier.
The SA571 is well suited for use in cellular radio and radio communications systems, modems, telephone, and satellite broadcast/receive audio systems.
FEATURES
•Complete compressor and expandor in one IChip
•Temperature compensated
•Greater than 110dB dynamic range
•Operates down to 6VDC
•System levels adjustable with external components
•Distortion may be trimmed out
•Dynamic noise reduction systems
•Voltage-controlled amplifier
PIN CONFIGURATION
D, and N Packages1
RECT CAP 1 |
1 |
|
16 |
RECT CAP 2 |
|
|
|
|
|
RECT IN 1 |
2 |
|
15 |
RECT IN 2 |
|
|
|
|
|
AG CELL IN 1 |
3 |
|
14 |
AG CELL IN 2 |
|
|
|
|
|
GND |
4 |
|
13 |
VCC |
|
|
|
|
|
INV. IN 1 |
5 |
|
12 |
INV. IN 2 |
|
|
|
|
|
RES. R3 1 |
6 |
|
11 |
RES. R3 2 |
OUTPUT 1 |
|
|
|
OUTPUT 2 |
7 |
|
10 |
||
|
|
|
|
|
|
|
|
|
|
THD TRIM 1 |
8 |
|
9 |
THD TRIM 2 |
|
|
|
|
|
TOP VIEW |
|
NOTE: |
|
1. SOL - Released in Large SO Package Only. |
SR00675 |
Figure 1. Pin Configuration
APPLICATIONS
•Cellular radio
•High level limiter
•Low level expandorÐnoise gate
•Dynamic filters
•CD Player
ORDERING INFORMATION
DESCRIPTION |
TEMPERATURE RANGE |
ORDER CODE |
DWG # |
|
|
|
|
16-Pin Plastic Small Outline Large (SOL) |
-40 to +85°C |
SA571D |
SOT162-1 |
|
|
|
|
16-Pin Plastic Dual In-Line Package (DIP) |
-40 to +85°C |
SA571N |
SOT38-4 |
BLOCK DIAGRAM
|
THD TRIM |
R3 |
|
INVERTER IN |
G IN |
R2 20k |
|
R3 20k |
|
VARIABLE |
|
|
± |
|
|
GAIN |
|
|
|
|
|
|
|
|
|
|
|
|
OUTPUT |
|
|
|
|
VREF |
|
|
|
R4 30k |
+ |
|
R1 10k |
|
1.8V |
|
RECT IN |
|
|
|
|
RECTIFIER |
|
|
|
|
|
|
|
|
|
|
RECT CAP |
|
SR00676 |
|
Figure 2. Block Diagram
1997 Aug 14 |
2 |
853-0812 18285 |
Philips Semiconductors |
Product specification |
|
|
|
|
Compandor |
SA571 |
|
|
|
|
ABSOLUTE MAXIMUM RATINGS
SYMBOL |
PARAMETER |
RATING |
UNITS |
|
|
|
|
VCC |
Maximum operating voltage |
18 |
VDC |
571 |
|||
TA |
Operating ambient temperature range |
-40 to +85 |
°C |
SA |
|||
|
|
|
|
PD |
Power dissipation |
400 |
mW |
AC ELECTRICAL CHARACTERISTICS
VCC = +6V, |
TA = 25°C; unless otherwise stated. |
|
|
|
|
|
|
|
|
|
|
|
LIMITS |
|
|
|
|
|
|
|
|
|
|
SYMBOL |
|
PARAMETER |
TEST CONDITIONS |
|
SA5715 |
|
UNITS |
|
|
|
|
MIN |
TYP |
MAX |
|
|
|
|
|
|
|
|
|
VCC |
|
Supply voltage |
|
6 |
|
18 |
V |
ICC |
|
Supply current |
No signal |
|
3.2 |
4.8 |
mA |
IOUT |
|
Output current capability |
|
±20 |
|
|
mA |
SR |
|
Output slew rate |
|
|
±.5 |
|
V/μs |
|
|
|
|
|
|
|
|
|
|
Gain cell distortion2 |
Untrimmed |
|
0.5 |
2.0 |
% |
|
|
Trimmed |
|
0.1 |
|||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
Resistor tolerance |
|
|
±5 |
±15 |
% |
|
|
|
|
|
|
|
|
|
|
Internal reference voltage |
|
1.65 |
1.8 |
1.95 |
V |
|
|
|
|
|
|
|
|
|
|
Output DC shift3 |
Untrimmed |
|
±30 |
±150 |
mV |
|
|
Expandor output noise |
No signal, 15Hz-20kHz1 |
|
20 |
60 |
μV |
|
|
Unity gain level6 |
1kHz |
-1.5 |
0 |
+1.5 |
dBm |
|
|
Gain change2, 4 |
|
|
±0.1 |
|
dB |
|
|
Reference drift4 |
|
|
+2, -25 |
+20, -50 |
mV |
|
|
Resistor drift4 |
|
|
+8, -0 |
|
% |
|
|
Tracking error (measured relative to |
Rectifier input, |
|
|
|
|
|
|
V2 = +6dBm, V1 = 0dB |
|
+0.2 |
|
|
|
|
|
value at unity gain) equals [VO - VO |
|
|
dB |
||
|
|
(unity gain)] dB - V2dBm |
V2 = -30dBm, V1 = 0dB |
|
+0.2 |
-1, +1.5 |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
Channel separation |
|
|
60 |
|
dB |
|
|
|
|
|
|
|
|
NOTES:
1.Input to V1 and V2 grounded.
2.Measured at 0dBm, 1kHz.
3.Expandor AC input change from no signal to 0dBm.
4.Relative to value at TA = 25°C.
5.Electrical characteristics for the SA571 only are specified over -40 to +85°C temperature range.
6.0dBm = 775mVRMS.
1997 Aug 14 |
3 |
Philips Semiconductors |
Product specification |
|
|
|
|
Compandor |
SA571 |
|
|
|
|
CIRCUIT DESCRIPTION
The SA571 compandor building blocks, as shown in the block diagram, are a full-wave rectifier, a variable gain cell, an operational amplifier and a bias system. The arrangement of these blocks in the IC result in a circuit which can perform well with few external components, yet can be adapted to many diverse applications.
The full-wave rectifier rectifies the input current which flows from the rectifier input, to an internal summing node which is biased at VREF. The rectified current is averaged on an external filter capacitor tied to the CRECT terminal, and the average value of the input current controls the gain of the variable gain cell. The gain will thus be proportional to the average value of the input signal for capacitively-coupled voltage inputs as shown in the following equation. Note that for capacitively-coupled inputs there is no offset voltage capable of producing a gain error. The only error will come from the bias current of the rectifier (supplied internally) which is less than 0.1μA.
|VIN VREF | avg
R1
| VIN | avg R1
The speed with which gain changes to follow changes in input signal levels is determined by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully filter low frequency signals. Any ripple on the gain control signal will modulate the signal passing through the variable gain cell. In an expander or compressor application, this would lead to third harmonic distortion, so there is a trade-off to be made between fast attack and decay times and distortion. For step changes in amplitude, the change in gain with time is shown by this equation.
G(t) (Ginitial Gfinal)e t
Gfinal ; 10k x CRECT
The variable gain cell is a current-in, current-out device with the ratio IOUT/IIN controlled by the rectifier. IIN is the current which flows from the G input to an internal summing node biased at VREF. The following equation applies for capacitively-coupled inputs. The output current, IOUT, is fed to the summing node of the op amp.
IIN |
|
VIN VREF |
|
VIN |
|
R2 |
R2 |
||||
|
|
|
A compensation scheme built into the G cell compensates for temperature and cancels out odd harmonic distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset voltages. The THD trim terminal provides a means for nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally compensated) has the non-inverting input tied to VREF, and the inverting input connected to the G cell output as well as brought out externally. A resistor, R3, is brought out from the summing node and allows compressor or expander gain to be determined only by internal components.
The output stage is capable of ±20mA output current. This allows a +13dBm (3.5VRMS) output into a 300Ω load which, with a series resistor and proper transformer, can result in +13dBm with a 600Ω output impedance.
A bandgap reference provides the reference voltage for all summing nodes, a regulated supply voltage for the rectifier and G cell, and a
bias current for the G cell. The low tempco of this type of reference provides very stable biasing over a wide temperature range.
The typical performance characteristics illustration shows the basic input-output transfer curve for basic compressor or expander circuits.
(dBm) |
+20 |
|
LEVEL |
+10 |
|
OUTPUT |
||
±10 |
||
|
0 |
|
EXPANDOR |
±30 |
|
|
±20 |
|
OR |
±40 |
|
LEVEL |
||
±50 |
||
INPUT |
||
±60 |
||
COMPRESSOR |
||
±70 |
||
|
±80 |
±40 |
±30 |
±20 |
±10 |
0 |
+10 |
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
SR00677
Figure 3. Basic Input-Output Transfer Curve
TYPICAL TEST CIRCUIT
|
VCC = 15V |
|
|
|
|
|
|
0.1μF |
10μF |
|
|
|
13 |
|
|
|
|
|
|
|
|
6.11 |
|
|
|
|
20k |
|
|
2.2μF |
20k |
|
|
|
|
V1 |
G |
|
|
|
|
|
|
|
|
||
|
|
|
7.10 |
VO |
|
3.14 |
|
|
|
||
|
|
|
|
|
|
|
|
|
VREF |
|
|
2.2 |
10k |
|
|
|
|
V2 |
|
|
30k |
|
|
2.15 |
|
|
|
|
|
|
|
|
|
|
|
|
4 |
1.16 |
5.12 |
8.9 |
|
|
|
2.2 |
8.2k |
200pF |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
SR00678 |
Figure 4. Typical Test Circuit
INTRODUCTION
Much interest has been expressed in high performance electronic gain control circuits. For non-critical applications, an integrated circuit operational transconductance amplifier can be used, but when high-performance is required, one has to resort to complex discrete circuitry with many expensive, well-matched components.
1997 Aug 14 |
4 |
Loading...