Philips N74F374DB, N74F374D, N74F373DB, N74F373D, N74F374N Datasheet
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FAST PRODUCTS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product specification |
1994 Dec 05 |
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F373/74F374 |
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74F373 Octal transparent latch (3-State) 74F374 Octal D-type flip-flop (3-State)
FEATURES
•8-bit transparent latch Ð 74F373
•8-bit positive edge triggered register Ð 74F374
•3-State outputs glitch free during power-up and power-down
•Common 3-State output register
•Independent register and 3-State buffer operation
•SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled
The 74F374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop's Q output.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is low, the data in the register appears at the outputs. When OE is high, the outputs
are in high impedance ªoffº state, which means they will neither drive nor load the bus.
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output.
When OE is high, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.
ORDERING INFORMATION
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TYPICAL |
TYPICAL SUPPLY |
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PROPAGATION |
CURRENT |
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DELAY |
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74F373 |
4.5ns |
35mA |
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TYPICAL SUPPLY |
TYPE |
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TYPICAL fmax |
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CURRENT |
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(TOTAL) |
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74F374 |
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165MHz |
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55mA |
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ORDER CODE |
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DESCRIPTION |
COMMERCIAL RANGE |
PKG DWG # |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
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20-pin plastic DIP |
N74F373N, N74F374N |
SOT146-1 |
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20-pin plastic SOL |
N74F373D, N74F374D |
SOT163-1 |
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20-pin plastic SSOP type II |
N74F373DB, N74374DB |
SOT399-1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS |
DESCRIPTION |
74F (U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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D0 - D7 |
Data inputs |
1.0/1.0 |
20μA/0.6mA |
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E (74F373) |
Enable input (active high) |
1.0/1.0 |
20μA/0.6mA |
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Output enable inputs (active low) |
1.0/1.0 |
20μA/0.6mA |
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OE |
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CP (74F374) |
Clock pulse input (active rising edge) |
1.0/1.0 |
20μA/0.6mA |
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Q0 - Q7 |
3-State outputs |
150/40 |
3.0mA/24mA |
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NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
December 5, 1994 |
2 |
853-0369 14383 |
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F373/74F374 |
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PIN CONFIGURATION ± 74F373 |
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PIN CONFIGURATION ± 74F374 |
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VCC |
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OE |
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20 |
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OE |
1 |
20 |
VCC |
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Q0 |
Q7 |
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Q0 |
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19 |
Q7 |
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19 |
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D0 |
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D7 |
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D0 |
3 |
18 |
D7 |
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3 |
18 |
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D1 |
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D6 |
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D1 |
4 |
17 |
D6 |
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4 |
17 |
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Q1 |
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Q6 |
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Q1 |
5 |
16 |
Q6 |
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5 |
16 |
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Q2 |
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Q5 |
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Q2 |
6 |
15 |
Q5 |
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6 |
15 |
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D2 |
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D5 |
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D2 |
7 |
14 |
D5 |
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7 |
14 |
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D3 |
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D4 |
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D3 |
8 |
13 |
D4 |
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8 |
13 |
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Q3 |
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Q4 |
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Q3 |
9 |
12 |
Q4 |
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9 |
12 |
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GND |
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CP |
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GND 10 |
11 |
E |
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10 |
11 |
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SF00250 |
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SF00253 |
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LOGIC SYMBOL ± 74F373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
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E |
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1 |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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2 |
5 |
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9 |
12 |
15 |
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19 |
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VCC = Pin 20
GND = Pin 10
SF00251
IEC/IEE SYMBOL ± 74F374
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
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CP |
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1 |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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2 |
5 |
6 |
9 |
12 |
15 |
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19 |
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VCC = Pin 20
GND = Pin 10
SF00254
IEC/IEEE SYMBOL ± 74F373
1 |
EN1 |
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11 |
EN2 |
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3 |
2D |
1 |
2 |
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4 |
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6 |
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9 |
13 |
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12 |
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14 |
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15 |
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17 |
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SF00252 |
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IEC/IEEE SYMBOL ± 74F374
1 |
EN1 |
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11 |
C2 |
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3 |
2D |
1 |
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7 |
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12 |
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14 |
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15 |
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17 |
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16 |
18 |
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19 |
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SF00255 |
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December 5, 1994 |
3 |
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F373/74F374 |
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LOGIC DIAGRAM FOR 74F373
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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3 |
4 |
7 |
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13 |
14 |
17 |
18 |
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D |
D |
D |
D |
D |
D |
D |
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D |
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E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
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E Q |
E |
11 |
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OE 1 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
VCC = Pin 20 |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
GND = Pin 10 |
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SF00256 |
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LOGIC DIAGRAM FOR 74F374
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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3 |
4 |
7 |
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13 |
14 |
17 |
18 |
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D |
D |
D |
D |
D |
D |
D |
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D |
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CP Q |
CP Q |
CP Q |
CP Q |
CP Q |
CP Q |
CP Q |
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CP Q |
CP |
11 |
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OE |
1 |
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VCC = Pin 20 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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GND = Pin 10 |
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SF00257 |
FUNCTION TABLE FOR 74F373
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INPUTS |
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INTERNAL |
OUTPUTS |
OPERATING MODE |
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OE |
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E |
Dn |
REGISTER |
Q0 - Q7 |
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L |
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H |
L |
L |
L |
Enable and read register |
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L |
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H |
H |
H |
H |
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L |
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↓ |
l |
L |
L |
Latch and read register |
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L |
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↓ |
h |
H |
H |
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L |
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L |
X |
NC |
NC |
Hold |
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H |
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L |
X |
NC |
Z |
Disable outputs |
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H |
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H |
Dn |
Dn |
Z |
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NOTES: |
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H |
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High-voltage level |
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h |
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High state must be present one setup time before the high-to-low enable transition |
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L |
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Low-voltage level |
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l |
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Low state must be present one setup time before the high-to-low enable transition |
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NC= |
No change |
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X |
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Don't care |
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Z |
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High impedance ªoffº state |
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↓ |
= |
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High-to-low enable transition |
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December 5, 1994 |
4 |
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