Philips N74F8960F, N74F8961N, N74F8961F, N74F8961A, N74F8960N Datasheet

	Philips Semiconductors FAST Products	Product specification
	Octal latched bidirectional Futurebus transceivers	74F8960/74F8961
	(3-State + open-collector)

FEATURES

•Octal latched transceiver

•Drives heavily loaded backplanes with equivalent load impedances down to 10Ω

•High drive (100mA) open collector drivers on B port

•Reduced voltage swing (1 volt) produces less noise and reduces power consumption

•High speed operation enhances performance of backplane buses and facilitates incident wave switching

•Compatible with IEEE futurebus standards

•Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity

•Controlled output ramp and multiple GND pins minimize ground bounce

•Glitch-free power up/down operation

DESCRIPTION

The 74F8960 and 74F8961 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired±OR bus. The B port inverting drivers are low±capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter.

The B port interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading.

Incident switching is employed, therefore BTL propagation delays are short. Although the

voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent.

BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.

The 74F8960 and 74F8961 A ports have TTL 3±state drivers and TTL receivers with a latch function. A separate High±level control input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC.

The 74F8961 is the non±inverting version of 74F8960.

TYPE	TYPICAL PROPAGATION DELAY	TYPICAL SUPPLY CURRENT( TOTAL)
74F8960	6.5ns	80mA
74F8961	6.5ns	80mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%, Tamb = 0°C to +70°C

28±pin plastic DIP (300 mil)1

N74F8960N, N748961N

28±pin PLCC1

N74F8960A, N74F8961A

NOTE: Thermal mounting techiques are recommended.

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

LOAD VALUE

HIGH/LOW

HIGH/LOW

A0 ± A8

PNP latched inputs

3.5/0.117

70μA/70μA

B0 ± B8

Data inputs with threshold circuitry

5.0/0.167

100μA/100μA

OEA

A output enable input (active high)

1.0/0.033

20μA/20μA

B output enable inputs (active low)

1.0/0.033

20μA/20μA

OEB0, OEB1

Latch enable input (active low)

1.0/0.033

20μA/20μA

LE

A0 ± A7

3±state outputs

150/40

3mA/24mA

B0 ± B7

Open collector outputs

OC/166.7

OC/100mA

NOTES:

1.One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

2.OC = Open collector.

December 19, 1990

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853-1120 01322

Philips Semiconductors FAST Products Product specification

Octal latched bidirectional Futurebus transceivers															74F8960/74F8961
(3-State + open-collector)
PIN CONFIGURATION				PIN CONFIGURATION PLCC									LOGIC SYMBOL
		74F8960					74F8960								74F8960
VCC 1		28	LE											3	5 6	7	9	10	12	13
OEA	2	27	B0		GND A0 OEA VCC LE					B0	B1
A0	3	26	B1		4	3	2	1	28	27	26
GND	4	25	GND	A1	5						25	GND		A0 A1 A2		A3 A4		A5	A6	A7
A1	5	24	B2	A2	6						24	B2	15	OEB0
A2	6	23	B3	A3	7						23	B3	2	OEA
A3	7	22	GND	GND	8		PLCC				22	GND	28	LE
													16	OEB1
GND	8	21	B4	A4	9						21	B4
A4	9	20	B5	A5	10						20	B5		B0 B1 B2		B3	B4 B5		B6 B7
A5	10	19	B6	GND	11						19	B6
GND 11		18	GND		12	13	14	15	16	17	18
A6	12	17	B7		A6	A7 VX OEB2 OEB1 B7 GND								27	26 24	23	21	20	19	17
			OEB1
A7	13	16
VX 14		15	OEB0										VCC = Pin 1, VX = Pin 14
													GND = Pin 4, 8, 11, 18, 22, 25

PIN CONFIGURATION											PIN CONFIGURATION PLCC																								LOGIC SYMBOL
		74F8961																	74F8961																								74F8961
VCC	1				28		LE																														3			5			6			7			9			10			12		13
OEA							B0
	2				27								GND A0 OEA VCC											LE			B0		B1
A0														4		3		2			1		28				27		26
	3				26		B1				A1
GND	4				25		GND					5																				25	GND				A0 A1 A2									A3 A4						A5			A6			A7
											A2
A1												6
	5				24		B2																									24	B2		15		OEB0
A2												7																					B3		2		OEA
	6				23		B3				A3																					23
A3																																			28		LE
	7				22		GND				GND	8								PLCC											22		GND		16		OEB1
GND											A4
	8				21		B4					9																				21	B4
A4							B5
	9				20						A5	10																				20	B5					B0 B1 B2									B3 B4					B5				B6 B7
A5	10				19		B6				GND	11																				19	B6
GND 11					18		GND
														12		13			14		15		16				17		18								27			26			24			23			21			20			19		17
A6	12				17		B7
														A6		A7 VX OEB2 OEB1 B7													GND
A7	13				16		OEB1
VX 14					15
							OEB0																												VCC = Pin 1, VX = Pin 14
																																			GND = Pin 4, 8, 11, 18, 22, 25

December 19, 1990

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Philips Semiconductors FAST Products Product specification

Octal latched bidirectional Futurebus transceivers					74F8960/74F8961
(3-State + open-collector)
IEC/IEEE SYMBOL FOR 74F8960			IEC/IEEE SYMBOL FOR 74F8961
		74F8960			74F8961
15	&		15	&
		EN2			EN2
16			16
28	C1		28	C1
2			2
	EN3			EN3
3	1D	27	3	1D	27
		2			2
	3		5	3
5		26			26
6		24	6		24
7		23	7		23
9		21	9		21
10		20	10		20
11		19	11		19
13		17	13		17

PIN DESCRIPTION

	SYMBOL					PINS	TYPE	NAME AND FUNCTION
	A0 ± A7					3, 5, 6, 7, 9, 10, 12, 13	I/O	PNP latched input/3±state output (with VX control option)
	B0 ± B7					27, 26, 24, 23, 21, 20, 19, 17	I/O	Data input with special threshold circuitry to reject noise/ open collector output, high
								current drive
						15	Input	Enables the B outputs when both pins are low
		OEB0
						16	Input	Enables the A outputs when high
		OEB1
						28	Input	Latched when high (a special feature is buillt in for proper enabling times)
			LE
		VX				14	Input	Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)

December 19, 1990

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Philips Semiconductors FAST Products Product specification

	Octal latched bidirectional Futurebus transceivers	74F8960/74F8961
	(3-State + open-collector)
	LOGIC DIAGRAM

		74F9860
OEB0 15
OEB1	16
OEA 2
LE	28
A0	3	Data	Q	27
		LE
A1	5	Data	Q	26
		LE
A2	6	Data	Q	24
		LE
A3	7	Data	Q	23
		LE
A4	9	Data	Q	21
		LE
A5 10		Data	Q	20
		LE
A6 12		Data	Q	19
		LE
A7 13		Data	Q	17
		LE

B0

B1

B2

B3

B4

B5

B6

B7

		74F9861
OEB0 15
OEB1	16
OEA 2
LE	28
A0	3	Data	Q	27
		LE
A1	5	Data	Q	26
		LE
A2	6	Data	Q	24
		LE
A3	7	Data	Q	23
		LE
A4	9	Data	Q	21
		LE
A5 10		Data	Q	20
		LE
A6 12		Data	Q	19
		LE
A7 13		Data	Q	17
		LE

B0

B1

B2

B3

B4

B5

B6

B7

VCC = Pin 1, VX = Pin 14, GND = Pin 4, 8, 11, 18, 22, 25

December 19, 1990

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