Philips N74ALS373D, N74ALS373DB, N74ALS373N, N74ALS374D, N74ALS374DB Datasheet

INTEGRATED CIRCUITS

74ALS373/74ALS374

Latch/flip±flop

Product specification	1991 Feb 08
IC05 Data Handbook

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Philips Semiconductors	Product specification
Latch/flip-flop	74ALS373/74ALS374

74ALS373 Octal transparent latch (3-State) 74ALS374 Octal D flip-flop (3-State)

FEATURES

•8-bit transparent latch ± 74ALS373

•8-bit positive edge triggered register ± 74ALS374

•3-State output buffers

•Common 3-State output register

•Independent register and 3-State buffer operation

		TYPICAL	TYPICAL
	TYPE		SUPPLY CURRENT
		PROPAGATION DELAY
			(TOTAL)
	74ALS373	6.0ns	14mA
		TYPICAL	TYPICAL
	TYPE		SUPPLY CURRENT
		fMAX
			(TOTAL)
	74ALS374	50MHz	17mA

ORDERING INFORMATION

		ORDER CODE
			DRAWING
	DESCRIPTION	COMMERCIAL RANGE
			NUMBER
		VCC = 5V ±10%,
		Tamb = 0°C to +70°C
	20-pin plastic DIP	74ALS373N, 74ALS374N	SOT146-1
	20-pin plastic SOL	74ALS373D, 74ALS374D	SOT163-1
	20-pin plastic SSOP	74ALS373DB, 74ALS374DB	SOT339-1
	Type II

DESCRIPTION

The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.

The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output.

When OE is High, the outputs are in High impedance ªoffº state, which means they will neither drive nor load the bus.

The 74ALS374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates.

The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

The active-Low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in High impedance ªoffº state, which means they will neither drive nor load the bus.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

	PINS			DESCRIPTION	74ALS (U.L.)	LOAD VALUE
					HIGH/LOW	HIGH/LOW
	D0 ± D7			Data inputs	1.0/1.0	20μA/0.1mA
	E (74ALS373)			Enable input (active-High)	1.0/1.0	20μA/0.1mA
				Output enable inputs (active-Low)	1.0/1.0	20μA/0.1mA
		OE
	CP (74ALS374)			Clock pulse input (active rising edge)	1.0/1.0	20μA/0.1mA
	Q0 ± Q7			3-State outputs	130/240	2.6mA/24mA

NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state.

1991 Feb 08

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853±1243 01670

Philips Semiconductors	Product specification
Latch/flip-flop	74ALS373/74ALS374

PIN CONFIGURATION ± 74ALS373																							PIN CONFIGURATION ± 74ALS374
																													1									20				VCC
																										OE
		OE				1									20			VCC
			Q0			2									19			Q7								Q0			2									19				Q7
			D0			3									18			D7								D0			3									18				D7
			D1			4									17			D6								D1			4									17				D6
			Q1			5									16			Q6								Q1			5									16				Q6
			Q2			6									15			Q5								Q2			6											15		Q5
			D2			7									14			D5								D2			7									14				D5
			D3			8									13			D4								D3			8									13				D4
			Q3			9									12			Q4								Q3			9									12				Q4
		GND 10													11			E							GND				10											11		CP
																					SF00250																								SF00253
LOGIC SYMBOL ± 74ALS373																							LOGIC SYMBOL ± 74ALS374
	3					4		7			8		13		14		17		18					3					4		7		8		13			14			17		18
			D0			D1			D2		D3		D4		D5		D6		D7							D0			D1		D2		D3		D4			D5			D6		D7
11		E																					11		CP
1		OE
																							1		OE
		Q0				Q1			Q2		Q3		Q4		Q5		Q6		Q7
																									Q0				Q1		Q2		Q3		Q4			Q5		Q6			Q7
	2					5		6			9		12		15		16		19					2					5		6		9		12			15		16			19
VCC = Pin 20																							VCC = Pin 20
																							GND = Pin 10
GND = Pin 10																					SF00251																								SF00254
IEC/IEEE SYMBOL ± 74ALS373																							IEC/IEEE SYMBOL ± 74ALS374
	1																							1
							EN1																							EN1
	11						EN2																	11							C1
	3																		2					3																			2
								2D					1																	2D					1
	4																		5					4																			5
	7																		6					7																			6
	8																		9					8																			9
	13																		12					13																			12
	14																		15					14																			15
	17																		16					17																			16
	18																		19		SF00252			18																			19		SC00098

1991 Feb 08

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Philips Semiconductors	Product specification
Latch/flip-flop	74ALS373/74ALS374

LOGIC DIAGRAM ± 74ALS373

	D0	D1	D2	D3	D4	D5	D6	D7
	3	4	7	8	13	14	17	18
	D	D	D	D	D	D	D		D
	E Q	E Q	E Q	E Q	E Q	E Q	E Q		E Q
E	11
OE 1
		2	5	6	9	12	15	16	19
VCC = Pin 20		Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
GND = Pin 10									SF00256

FUNCTION TABLE ± 74ALS373

					INPUTS			INTERNAL REGISTER	OUTPUTS	OPERATING MODE
					E		Dn		Q0 ± Q7
		OE
		L			H		L	L	L	Enable and read register
		L			H		H	H	H
		L			↓		l	L	L	Latch and read register
		L			↓		h	H	H
		L			L		X	NC	NC	Hold
		H			L		X	NC	Z	Disable outputs
		H			H		Dn	Dn	Z
H	=	High-voltage level
h	=	High state must be present one setup time before the High-to-Low enable transition
L	=	Low-voltage level
l	=	Low state must be present one setup time before the High-to-Low enable transition
NC=		No change
X	=	Don't care
Z	=	High impedance ªoffº state
↓ =		High-to-Low enable transition

1991 Feb 08

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