Philips N74ALS161BD, N74ALS161BDB, N74ALS161BN, N74ALS163BD, N74ALS163BDB Datasheet

INTEGRATED CIRCUITS

74ALS161B/74ALS163B

4-bit binary counter

Product specification

1991 Feb 08

IC05 Data Handbook

m n r

Philips Semiconductors		Product specification
4-bit binary counter		74ALS161B/74ALS163B
74ALS161B	4-bit binary counter, asynchronous reset
74ALS163B	4-bit binary counter, synchronous reset

FEATURES

•Synchronous counting and loading

•Two count enable inputs for n-bit cascading

•Positive edge-triggered clock

•Asynchronous reset (74ALS161B)

•Synchronous reset (74ALS163B)

•High speed synchronous expansion

•Typical count rate of 140MHz

		TYPICAL
TYPE	TYPICAL fMAX	SUPPLY CURRENT
		(TOTAL)
74ALS161B	140MHz	10mA
74ALS163B	140MHz	10mA

ORDERING INFORMATION

		ORDER CODE
			DRAWING
	DESCRIPTION	COMMERCIAL RANGE
		VCC = 5V ±10%,	NUMBER
		Tamb = 0°C to +70°C
	16-pin plastic DIP	74ALS161BN, 74ALS163BN	SOT38-4
	16-pin plastic SO	74ALS161BD, 74ALS163BD	SOT109-1
	16-pin plastic SSOP	74ALS161BDB,	SOT338-1
	Type II	74ALS163BDB

DESCRIPTION

Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered.

The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 ± D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs.

A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 ± Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function).

For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 ± Q3) to Low levels after the next positive-going transition on the clock (CP) input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at CP, PE, CET and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1).

The carry look-ahead simplifies serial cascading of the counters. Both count enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2).

The TC output is subjected to decoding spikes due to internal race conditions, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

	PINS					DESCRIPTION	74ALS (U.L.)	LOAD VALUE
							HIGH/LOW	HIGH/LOW
	D0 ± D3					Data inputs	1.0/1.0	20μA/0.1mA
	CEP					Count enable parallel input (active-Low)	1.0/1.0	20μA/0.1mA
	CET					Count enable trickle input (active-Low)	1.0/1.0	20μA/0.1mA
		CP				Clock input (active rising edge)	1.0/1.0	20μA/0.1mA
						Parallel enable input (active-Low)	1.0/1.0	20μA/0.1mA
		PE
						Asynchronous master reset input (active-Low) for 74ALS161B	1.0/1.0	20μA/0.1mA
		MR
						Asynchronous reset input (active-Low) for 74ALS163B	1.0/1.0	20μA/0.1mA
		SR
	Q0 ± Q3					Flip-flop outputs	20/80	0.4mA/8mA
		TC				Terminal count output (active-Low)	20/80	0.4mA/8mA

NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state.

1991 Feb 08

2

853±1350 01670

Philips Semiconductors	Product specification
4-bit binary counter	74ALS161B/74ALS163B

STATE DIAGRAM

0 1 2 3 4

15	5
14	6
13	7

12 11 10 9 8

SF00664

APPLICATIONS

VCC
	PE	D0	D1	D2	D3
	CEP
	CET 74ALS163B				TC
CLOCK	CP
	SR	Q0	Q1	Q2	Q3

SC00086

Figure 1. Maximum Count Modifying Scheme

Terminal Count = 6

H H = Enable count

or

L

L = Disable count

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

PE D0 D1 D2 D3

CEP

74ALS163B

CEP

74ALS163B

CEP

74ALS163B

CEP

74ALS163B

CEP

74ALS163B

CET

TC

CET

TC

CET

TC

CET

TC

CET

TC

CP

CP

CP

CP

CP

SR Q0 Q1 Q2 Q3

SR

Q0 Q1 Q2

Q3

SR

Q0 Q1 Q2

Q3

SR

Q0 Q1 Q2

Q3

SR

Q0 Q1 Q2

Q3

CP

SC00087

Figure 2. Synchronous Multistage Counting Scheme

1991 Feb 08

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Philips Semiconductors	Product specification
4-bit binary counter	74ALS161B/74ALS163B

PIN CONFIGURATION ± 74ALS161B									PIN CONFIGURATION ± 74ALS163B
	MR		1		16	VCC				SR		1		16	VCC
	CP					TC			CP						TC
			2		15							2		15
	D0					Q0				D0					Q0
			3		14							3		14
	D1					Q1				D1					Q1
			4		13							4		13
	D2					Q2				D2					Q2
			5		12							5		12
	D3					Q3				D3					Q3
			6		11							6		11
CEP						CET			CEP						CET
			7		10							7		10
GND									GND
			8		9		PE					8		9		PE
								SF00656									SF00657

LOGIC SYMBOL ± 74ALS161B

							3		4		5		6
9			PE				D0		D1		D2			D3
7			CEP												TC		15
10			CET
2			CP
1			MR				Q0		Q1		Q2		Q3
VCC = Pin 16							14		13		12		11
GND = Pin 8																		SF00658
IEC/IEEE SYMBOL ± 74ALS161B
		1			R				CTR DIV 16
		9
					M1
		7
					G3
		10
					G4
		2
						C2 /1,3,4+
		3															14
				1,2 D
		4															13
		5															12
6																	11
																	15
												4 CT=15

LOGIC SYMBOL ± 74ALS163B

					3				4		5		6
9			PE				D0		D1		D2			D3
7			CEP												TC		15
10			CET
2			CP
1			SR				Q0		Q1		Q2		Q3
VCC = Pin 16					14				13		12		11
GND = Pin 8																		SF00659
IEC/IEEE SYMBOL ± 74ALS163B
		1			2R				CTR DIV 16
		9
					M1
		7
					G3
		10
					G4
		2
						C2 /1,3,4+
		3															14
					1,2 D
		4															13
		5															12
6																	11
																	15
												4 CT=15

SF00660

SF00661

1991 Feb 08

4

Philips Semiconductors	Product specification
4-bit binary counter	74ALS161B/74ALS163B

LOGIC DIAGRAM ± 74ALS161B

2
CP
1
MR
9
PE
10
CET
7
CEP
3
D0
D	R Q
CP	Q	14
		Q0
4
D1
D	R Q
CP	Q	13
		Q1
5
D2
D	R Q
CP	Q	12
		Q2
6
D3
D	R Q
CP	Q	11
		Q3
		15
		TC
VCC = Pin 16
GND = Pin 8		SF00662

MODE SELECTION FUNCTION TABLE ± 74ALS161B

INPUTS

OUTPUTS

OPERATING MODE

MR

CP

CEP

CET

PE

Dn

Qn

TC

L

X

X

X

X

X

L

L

Reset (clear)

H

↑

X

X

l

l

L

L

Parallel load

H

↑

X

X

l

h

H

(a)

H

↑

h

h

h

X

count

(a)

Count

h

X

l

X

h

X

qn

(a)

Hold (do nothing)

h

X

X

l

h

X

qn

L

H

=

High-voltage level

h

=

High state must be present one setup time before the Low-to-High clock transition

L

=

Low-voltage level

l

=

Low state must be present one setup time before the Low-to-High clock transition

qn =

Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition

X

=

Don't care

(a) =

The output is High when CET is High and the counter is at terminal count (HHHH)

↑

=

Low-to-High clock transition

1991 Feb 08

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