Philips N74F646D, N74F646N, N74F646AN, N74F648AD, N74F646AD Datasheet
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INTEGRATED CIRCUITS
74F646, 74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648, 74F648A
Octal transceiver/register, inverting
(3-State)
Product specification |
1990 Sep 25 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Transceivers/registers |
74F646/A/74F648/A |
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FEATURES
•Combines 74F245 and two 74F374 type functions in one chip
•High impedance base inputs for reduced loading (70μA in high and low states)
•Independent registers for A and B buses
•Multiplexed real-time and stored data
•Choice of non-inverting and inverting data paths
•Controlled ramp outputs for 74F646A/74F648A
•3-state outputs
•300 mil wide 24-pin slim dip package
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers consist of bus transceiver circuits with 3±state outputs, D±type flip±flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both.
The select (SAB, SBA) pins determine whether data is stored or transferred through the device in real±time. The DIR determines which bus will receive data when the OE is active low. In the isolation mode (OE = high), data from bus A may be stored in the B register and/or data from bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B may be driven at a time.
TYPE |
TYPICAL fmax |
TYPICAL SUPPLY CURRENT ( TOTAL) |
74F646/74F648 |
115MHz |
140mA |
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74F646A/74F648A |
185MHz |
105mA |
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ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
COMMERCIAL RANGE |
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PKG DWG # |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
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24±pin plastic slim DIP |
N74F646N, N74F646AN, N74F648N, N74F648AN |
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SOT222-1 |
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(300mil) |
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24±pin plastic SOL |
N74F646D, N74F646AD, N74F648D, N74F648AD |
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SOT137-1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE |
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PINS |
DESCRIPTION |
74F (U.L.) HIGH/ |
LOAD VALUE HIGH/ |
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LOW |
LOW |
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A0 ± A7, B0 ± B7 |
A and B inputs |
3.5/0.116 |
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70μA/70μA |
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CPAB |
A±to±B clock input |
1.0/0.033 |
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20μA/20μA |
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CPBA |
B±to±A clock input |
1.0/0.033 |
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20μA/20μA |
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SAB |
A±to±B select input |
1.0/0.033 |
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20μA/20μA |
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SBA |
B±to±A select input |
1.0/0.033 |
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20μA/20μA |
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DIR |
Data flow directional control enable input |
1.0/0.033 |
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20μA/20μA |
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Output enable input |
1.0/0.033 |
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20μA/20μA |
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OE |
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A0 ± A7, B0 ± B7 |
A, B outputs for N74F646A/N74F648A |
750/80 |
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15mA/48mA |
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A0 ± A7, B0 ± B7 |
A, B outputs for N74F646/N74F648 |
750/106.7 |
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15mA/64mA |
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NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
1990 Sep 25 |
2 |
853-1124 00515 |
Philips Semiconductors |
Product specification |
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Transceivers/registers |
74F646/A/74F648/A |
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PIN CONFIGURATION
74F646/646A
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CPAB |
1 |
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24 |
VCC |
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SAB |
2 |
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23 |
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CPBA |
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DIR |
3 |
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22 |
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SBA |
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A0 |
4 |
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21 |
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OE |
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A1 |
5 |
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20 |
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B0 |
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A2 |
6 |
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19 |
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B1 |
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A3 |
7 |
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18 |
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B2 |
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A4 |
8 |
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17 |
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B3 |
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A5 |
9 |
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16 |
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B4 |
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A6 |
10 |
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15 |
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B5 |
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A7 |
11 |
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14 |
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B6 |
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GND |
12 |
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13 |
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B7 |
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SF00386 |
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LOGIC SYMBOL
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74F646/646A |
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4 |
5 |
6 |
7 |
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9 |
10 |
11 |
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A0 |
A1 |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
1 |
CPAB |
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2 |
SAB |
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3 |
DIR |
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23 |
CPBA |
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22 |
SBA |
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21 |
OE |
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B0 |
B1 |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
VCC = Pin 24 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
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GND = Pin 12
SF00387
IEC/IEEE SYMBOL
74F646/646A
21
G3
3
3 EN1 [BA]
3 EN2 [AB]
23
C4
22
G5
1
C6
2
G7
4 |
1 |
5 |
20 |
4D |
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1 |
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5 |
1 |
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6D |
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7 |
1 |
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7 |
2 |
5 |
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19 |
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6 |
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18 |
7 |
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17 |
8 |
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16 |
9 |
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15 |
/ |
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10 |
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14 |
11 |
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13 |
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SF00388 |
LOGIC DIAGRAM
21 |
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74F646/646A |
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OE |
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DIR3 |
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CPBA23 |
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22 |
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SBA |
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CPAB1 |
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2 |
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SAB |
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I |
of 8 |
channels |
1D |
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C1 |
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4 |
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20 |
A0 |
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1D |
B0 |
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C1 |
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VCC = Pin 24 |
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to 7 other channels |
SF00393 |
GND = Pin 12 |
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1990 Sep 25 |
3 |
Philips Semiconductors |
Product specification |
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Transceivers/registers |
74F646/A/74F648/A |
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PIN CONFIGURATION
74F648/648A
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CPAB |
1 |
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24 |
VCC |
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SAB |
2 |
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23 |
CPBA |
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DIR |
3 |
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22 |
SBA |
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A0 |
4 |
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21 |
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OE |
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A1 |
5 |
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20 |
B0 |
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A2 |
6 |
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19 |
B1 |
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A3 |
7 |
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18 |
B2 |
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A4 |
8 |
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17 |
B3 |
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A5 |
9 |
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16 |
B4 |
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A6 |
10 |
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15 |
B5 |
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A7 |
11 |
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14 |
B6 |
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GND |
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12 |
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13 |
B7 |
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SF00389 |
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LOGIC SYMBOL
74F648/648A
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
A0 A1 A2 A3 A4 A5 A6 A7
1CPAB
2SAB
3DIR
23 |
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CPBA |
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22 |
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SBA |
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21 |
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OE |
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B0 |
B1 |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
20 19 18 17 16 15 14 13
VCC = Pin 24
GND = Pin 12
SF00390
IEC/IEEE SYMBOL
74F648/648A
21
G3
3
3 EN1 [BA]
3 EN2 [AB]
23
C4
22
G5
1
C6
2
G7
4 |
1 |
5 |
20 |
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4D |
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1 |
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5 |
1 |
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6D |
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7 |
1 |
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1 |
7 |
2 |
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19 |
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6 |
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18 |
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7 |
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17 |
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8 |
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16 |
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9 |
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15 |
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10 |
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14 |
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11 |
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13 |
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SF00391 |
LOGIC DIAGRAM
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21 |
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74F648/648A |
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OE |
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DIR |
3 |
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CPBA |
23 |
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SBA |
22 |
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1 |
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CPAB 2 |
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SAB |
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I |
of 8 |
channels |
1D |
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C1 |
A0 |
4 |
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20 |
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1D |
B0 |
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C1 |
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to 7 other |
channels |
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SF00400 |
1990 Sep 25 |
4 |
Philips Semiconductors |
Product specification |
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Transceivers/registers |
74F646/A/74F648/A |
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FUNCTION TABLE
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INPUTS |
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DATA I/O |
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OPERATING MODE |
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DIR |
CPAB |
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CPBA |
SAB |
SBA |
An |
Bn |
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74F646/74F646A |
74F648/74F648A |
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OE |
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X |
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X |
↑ |
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X |
X |
Input |
Unspecified* |
Store A, B unspecified* |
Store A, B unspecified* |
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X |
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↑ |
X |
X |
Unspecified* |
Input |
Store B, A unspecified* |
Store B, A unspecified* |
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H |
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X |
↑ |
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↑ |
X |
X |
Input |
Input |
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Store A and B data |
Store A and B data |
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H |
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X |
H or L |
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H or L |
X |
X |
Input |
Input |
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Isolation, hold storage |
Isolation, hold storage |
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L |
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L |
X |
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X |
X |
L |
Output |
Input |
Real time B data to A bus |
Real time |
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data to A bus |
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B |
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L |
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L |
X |
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H or L |
X |
H |
Output |
Input |
Stored B data to A bus |
Stored |
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data to A bus |
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B |
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L |
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H |
X |
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X |
L |
X |
Input |
Output |
Real time A data to B bus |
Real time |
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data to B bus |
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A |
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L |
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H |
H or L |
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X |
H |
X |
Input |
Output |
Stored A data to B bus |
Stored |
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data to B bus |
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A |
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NOTES: |
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1. |
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H |
= |
High±voltage level |
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2. |
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L |
= |
Low±voltage level |
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3. |
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X |
= |
Don't care |
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4. |
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↑ |
= |
Low±to±high clock transition |
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and DIR inputs. Data input functions are |
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5. |
* |
= |
The data output function may be enabled or disabled by various signals at the |
OE |
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always enabled, i.e., data at the bus pins will be stored on every low±to±high transition of the clock. |
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ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL |
PARAMETER |
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RATING |
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UNIT |
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VCC |
Supply voltage |
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±0.5 to +7.0 |
V |
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VIN |
Input voltage |
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±0.5 to +7.0 |
V |
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IIN |
Input current |
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±30 to +5 |
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mA |
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VOUT |
Voltage applied to output in high output state |
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±0.5 to V |
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V |
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CC |
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IOUT |
Current applied to output in low output state |
74F646A, 74F648A |
72 |
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mA |
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74F646, 74F648 |
128 |
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mA |
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T |
Operating free air temperature range |
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0 to +70 |
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° |
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amb |
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C |
T |
Storage temperature range |
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±65 to +150 |
° |
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stg |
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C |
RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
PARAMETER |
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LIMITS |
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UNIT |
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MIN |
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NOM |
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MAX |
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VCC |
Supply voltage |
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4.5 |
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5.0 |
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5.5 |
V |
VIH |
High±level input voltage |
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2.0 |
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V |
VIL |
Low±level input voltage |
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0.8 |
V |
IIk |
Input clamp current |
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±18 |
mA |
IOH |
High±level output current |
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±15 |
mA |
IOL |
Low±level output current |
74F646A, 74F648A |
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48 |
mA |
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74F646, 74F648 |
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64 |
mA |
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T |
Operating free air temperature range |
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0 |
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+70 |
° |
amb |
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C |
1990 Sep 25 |
5 |
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