Philips N74F241AD, N74F240AD, N74F241N, N74F241D, N74F241AN Datasheet
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INTEGRATED CIRCUITS
74F240/74F240A
Octal inverter buffer (3-State)
74F241/74F241A
Octal buffer (3-State)
Product specification |
1001 Jan 02 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Buffers |
74F240/74F240A/ |
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74F241/74F241A |
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FEATURES
•Octal bus interface
•3-State buffer outputs sink 64mA
•15mA source current
•Guaranteed output skew less than 2.0ns (74F240A/74F241A)
•Reduced ground bounce (74F240A/74F241A)
•Reduced ICC (74F241A only)
•Reduced loading (74F240A IIL = 100μA, 74F241A IIL = 40μA)
DESCRIPTION
The 74F240 and 74F241 are octal buffers that are ideal for driving bus lines of buffer memory address registers. The outputs are all capable of sinking 64mA and sourcing up to 15mA. The device features two output enables, each controlling four of the 3±state outputs.
The 74F240A and 74F241A are functionally equivalent to their non±A counterparts. They have been designed to reduce effects of ground noise. Other advantages are noted in the features.
TYPE |
TYPICAL PROPAGATION DELAY |
TYPICAL SUPPLY CURRENT (TOTAL) |
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74F240 |
4.3ns |
37mA |
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74F240A |
3.8ns |
40mA |
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74F241 |
5.0ns |
53mA |
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74F241A |
4.5ns |
32mA |
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ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
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COMMERCIAL RANGE |
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PKG DWG # |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
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20±pin plastic DIP |
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N74F240N, N74F240AN, N74F241N, N74F241AN |
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SOT146-1 |
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20±pin plastic SOL |
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N74F240D, N74F240AD, N74F241D, N74F241AD |
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SOT163-1 |
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20-pin plastic SSOP II |
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N74F240DB |
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SOT339-1 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE |
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PINS |
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DESCRIPTION |
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74F (U.L.) |
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LOAD VALUE |
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HIGH/LOW |
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HIGH/LOW |
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Data inputs (74F240) |
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1.0/1.67 |
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20μA/1.0mA |
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Ian, Ibn |
Data inputs (74F240A) |
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1.0/0.167 |
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20μA/100μA |
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Data inputs (74F241) |
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1.0/2.67 |
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20μA/1.6mA |
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Data inputs (74F241A) |
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1.0/0.067 |
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20μA/40μA |
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Output enable inputs (active low) (74F240) |
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1.0/0.33 |
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20μA/0.2mA |
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OEa, OEb |
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Output enable inputs (active low) (74F240A) |
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1.0/0.167 |
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20μA/100μA |
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Output enable input (74F241) |
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1.0/1.67 |
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20μA/1.0mA |
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OEa, OEb |
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Output enable input (74F241A) |
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1.0/0.067 |
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20μA/40μA |
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Yan, Ybn |
Data outputs (74F241, 74F241A) |
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750/106.7 |
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15mA/64mA |
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Data outputs (74F240, 74F240A) |
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750/106.7 |
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15mA/64mA |
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Yan, Ybn |
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Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
January 2, 1991 |
2 |
853±0355 01345 |
Philips Semiconductors |
Product specification |
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Buffers
74F240/74F240A/
74F241/74F241A
PIN CONFIGURATION FOR 74F240/74F240A
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VCC |
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OEa |
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20 |
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Ia0 |
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19 |
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OEb |
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3 |
18 |
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Yb0 |
Ya0 |
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Ia1 |
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17 |
Ib0 |
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16 |
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Yb1 |
Ya1 |
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Ia2 |
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15 |
Ib1 |
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7 |
14 |
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Yb2 |
Ya2 |
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Ia3 |
8 |
13 |
Ib2 |
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9 |
12 |
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Yb3 |
Ya3 |
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GND |
10 |
11 |
Ib3 |
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SF00320 |
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LOGIC SYMBOL FOR 74F240/74F240A
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Ia0 |
Ia1 |
Ia2 |
Ia3 |
Ib0 |
Ib1 |
Ib2 |
Ib3 |
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OEa |
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19 |
OEb |
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Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3 |
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18 |
16 |
14 |
12 |
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5 |
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VCC = Pin 20
GND = Pin 10
SF00321
IEC/IEEE SYMBOL FOR 74F240/74F240A
1 |
EN1 |
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19 |
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EN2 |
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2 |
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2D |
1 |
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18 |
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4 |
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16 |
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14 |
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SF00322 |
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LOGIC DIAGRAM FOR 74F240/74F240A
2 |
18 |
Ya0 |
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3 |
Ia0 |
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Ib0 |
Yb0 |
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4 |
16 |
Ya1 |
15 |
5 |
Ia1 |
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Ib1 |
Yb1 |
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6 |
14 |
Ya2 |
13 |
7 |
Ia2 |
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Ib2 |
Yb2 |
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8 |
12 |
Ya3 |
11 |
9 |
Ia3 |
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Ib3 |
Yb3 |
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OEa 1 |
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OEb 10 |
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VCC = Pin 20
GND = Pin 10
SF00323
FUNCTION TABLE FOR 74F240/74F240A
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INPUTS |
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OUTPUTS |
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OEa |
Ia |
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OEb |
Ib |
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Ya |
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Yb |
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L |
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L |
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H |
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H |
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H |
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H |
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X |
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Z |
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Z |
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Notes to function table for 74F240/74F240A |
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H |
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High voltage level |
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L |
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Low voltage level |
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X |
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Don't care |
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Z |
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High impedance ºoffº state |
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January 2, 1991 |
3 |
Philips Semiconductors |
Product specification |
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Buffers
74F240/74F240A/
74F241/74F241A
PIN CONFIGURATION FOR 74F241/74F241A
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20 |
VCC |
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OEa |
1 |
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Ia0 |
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19 |
OEb |
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Yb0 |
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18 |
Ya0 |
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Ia1 |
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17 |
Ib0 |
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Yb1 |
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16 |
Ya1 |
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Ia2 |
6 |
15 |
Ib1 |
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Yb2 |
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14 |
Ya2 |
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Ia3 |
8 |
13 |
Ib2 |
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Yb3 |
9 |
12 |
Ya3 |
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GND |
10 |
11 |
Ib3 |
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SF00324 |
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LOGIC SYMBOL FOR 74F241/74F241A
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2 |
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6 |
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17 |
15 |
13 |
11 |
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Ia0 |
Ia1 |
Ia2 |
Ia3 |
Ib0 |
Ib1 |
Ib2 |
Ib3 |
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1 |
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OEa |
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19 |
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OEb |
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Ya0 |
Ya1 Ya2 |
Ya3 Yb0 |
Yb1 Yb2 |
Yb3 |
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18 |
16 |
14 |
12 |
3 |
5 |
7 |
9 |
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VCC = Pin 20
GND = Pin 10
SF00325
IEC/IEEE SYMBOL FOR 74F241/74F241A
1
EN1
19
EN2
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18 |
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2D |
1 |
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16 |
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14 |
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12 |
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15 |
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SF00326 |
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LOGIC DIAGRAM FOR 74F241/74F241A
Ia0 |
2 |
18 |
Ya0 |
Ib0 |
17 |
3 |
Yb0 |
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Ia1 |
4 |
16 |
Ya1 |
Ib1 |
15 |
5 |
Yb1 |
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Ia2 |
6 |
14 |
Ya2 |
Ib2 |
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7 |
Yb2 |
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Ia3 8 |
12 |
Ya3 |
Ib3 |
11 |
9 |
Yb3 |
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OEa |
1 |
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OEb |
10 |
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VCC = Pin 20
GND = Pin 10
SF00327
FUNCTION TABLE FOR 74F241/74F241A
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INPUTS |
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OUTPUTS |
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Ia |
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OEb |
Ib |
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Ya |
Yb |
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OEa |
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L |
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L |
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H |
L |
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L |
L |
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L |
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H |
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H |
H |
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H |
H |
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H |
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X |
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L |
X |
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Z |
Z |
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Notes to function table for 74F241/74F241A |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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X |
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Don't care |
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Z |
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High impedance ºoffº state |
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January 2, 1991 |
4 |
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