Philips N74F574N, N74F574D, N74F573N, N74F573D, N74F573DB Datasheet

INTEGRATED CIRCUITS

74F573

Octal transparent latch (3-State)

74F574

Octal transparent latch (3-State)

Product specification

1989 Oct 16

IC15 Data Handbook

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Philips Semiconductors	Product specification
Latch/flip-flop	74F573/74F574

74F573 Octal Transparent Latch (3-State)

74F574 Octal D Flip-Flop (3-State)

FEATURES

•74F573 is broadside pinout version of 74F373

•74F574 is broadside pinout version of 74F374

•Inputs and Outputs on opposite side of package allow easy interface to Microprocessors

•Useful as an Input or Output port for Microprocessors

•3-State Outputs for Bus interfacing

•Common Output Enable

•74F563 and 74F564 are inverting version of 74F573 and 74F574 respectively

•3-State Outputs glitch free during power-up and power-down

•These are High-Speed replacements for N8TS805 and N8TS806

DESCRIPTION

The 74F573 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates.

The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.

The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition.

The 74F574 is functionally identical to the 74F374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocesors.

It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.

		TYPICAL	TYPICAL SUPPLY
	TYPE		CURRENT
		PROPAGATION DELAY
			(TOTAL)
	74F573	5.0ns	35mA
			TYPICAL SUPPLY
	TYPE	TYPICAL fMAX	CURRENT
			(TOTAL)
	74F574	180MHz	50mA

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent to the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.

ORDERING INFORMATION

	COMMERCIAL RANGE
DESCRIPTION	VCC = 5V ±10%,	PKG DWG #
	Tamb = 0°C to +70°C
20-Pin Plastic DIP	N74F573N, N74F574N	SOT146-1
20-Pin Plastic SOL	N74F573D, N74F574D	SOT163-1
20-Pin Plastic SSOP	N74F573DB	SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

		PINS	DESCRIPTION	74F (U.L.)	LOAD VALUE
				HIGH/LOW	HIGH/LOW
	D0 - D7		Data inputs	1.0/1.0	20μA/0.6mA
	E (74F573)		Latch Enable input (active falling edge)	1.0/1.0	20μA/0.6mA
			Output Enable input (active Low)	1.0/1.0	20μA/0.6mA
	OE
	CP (74F574)		Clock Pulse input (active rising edge)	1.0/1.0	20μA/0.6mA
	Q0 - Q7		3-State outputs	150/40	3.0mA/24mA

NOTE: One (1.0) FAST Unit Load is defined as: 20μA in the High state and 0.6mA in the Low state.

1989 Oct 16

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853-0083 97897

Philips Semiconductors	Product specification
Latch/flip-flop	74F573/74F574

PIN CONFIGURATION ± 74F573						PIN CONFIGURATION ± 74F574
		1	20	VCC				1	20	VCC
	OE						OE
D0		2	19	Q0		D0		2	19	Q0
D1		3	18	Q1		D1		3	18	Q1
D2		4	17	Q2		D2		4	17	Q2
D3		5	16	Q3		D3		5	16	Q3
D4		6	15	Q4		D4		6	15	Q4
D5		7	14	Q5		D5		7	14	Q5
D6		8	13	Q6		D6		8	13	Q6
D7		9	12	Q7		D7		9	12	Q7
GND		10	11	E		GND		10	11	CP
			SF01073						SF01074

LOGIC SYMBOL ± 74F573

		2			3		4		5		6		7		8		9
				D0	D1		D2		D3		D4		D5		D6		D7
11		E
1		OE
			Q0		Q1		Q2		Q3		Q4		Q5		Q6		Q7
		19			18		17		16		15		14		13		12
VCC=Pin 20
GND=Pin 10																	SF01075
LOGIC SYMBOL (IEEE/IEC) ± 74F573
		1
							EN1
		11
							EN2
															19
		2
							2D				1
		3													18
		4													17
															16
		5
															15
		6
															14
		7
															13
		8
															12
		9

LOGIC SYMBOL ± 74F574

		2			3		4			5		6			7		8			9
		D0			D1		D2			D3		D4			D5		D6			D7
11		CP
1		OE
		Q0			Q1		Q2			Q3		Q4			Q5		Q6			Q7
		19			18		17			16		15			14		13			12
VCC=Pin 20
GND=Pin 10																				SF01076
LOGIC SYMBOL (IEEE/IEC) ± 74F574
				1
								EN1
				11
									C2
				2													19
								2D				1
				3													18
		4															17
																	16
		5
																	15
		6
		7															14
																	13
		8
																	12
		9

SF01077

SF01078

1989 Oct 16

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Philips Semiconductors	Product specification
Latch/flip-flop	74F573/74F574

LOGIC DIAGRAM ± 74F573

	D0	D1	D2	D3	D4	D5	D6		D7
	2	3	4	5	6	7	8		9
	D	D	D	D	D	D	D		D
	E Q	E Q	E Q	E Q	E Q	E Q	E Q		E Q
E	11
OE	1
		19	18	17	16	15	14	13	12
VCC=Pin 20		Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
GND=Pin 10
									SF01079

FUNCTION TABLE ± 74F573

					INPUTS			INTERNAL		OUTPUTS	OPERATING MODES
		OE			E		Dn	REGISTER		Q0 ± Q7
		L			H		L	L		L	Load and read register
		L			H		H	H		H
		L			↓		l	L		L	Latch and read register
		L			↓		h	H		H
		L			L		X	NC		NC	Hold
		H			L		X	NC		Z	Disable outputs
		H			H		Dn	Dn		Z
H	=	High voltage level
h	=	High voltage level one setup time prior to the High-to-Low E transition
L	=	Low voltage level
l	=	Low voltage level one setup time prior to the High-to-Low E transition
NC=		No change
X	=	Don't care
Z	=	High impedance ªoffº state
↓ =		High-to-Low E transition

LOGIC DIAGRAM ± 74F574

D0

D1

D2

D3

D4

D5

D6

D7

2

3

4

5

6

7

8

9

D

D

D

D

D

D

D

D

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

Q

CP

11

OE

1

19

18

17

16

15

14

13

12

VCC=Pin 20

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

GND=Pin 10

SF01080

1989 Oct 16

4

Philips Semiconductors	Product specification
Latch/flip-flop	74F573/74F574

FUNCTION TABLE ± 74F574

					INPUTS			INTERNAL	OUTPUTS	OPERATING MODES
		OE			CP		Dn	REGISTER	Q0 ± Q7
		L			↑		l	L	L	Load and read register
		L			↑		h	H	H
		L			↑		X	NC	NC	Hold
		H			↑		Dn	Dn	Z	Disable outputs
H	=	High voltage level
h	=	High voltage level one setup time prior to the Low-to-High clock transition
L	=	Low voltage level
l	=	Low voltage level one setup time prior to the Low-to-High clock transition
NC=		No change
X	=	Don't care
Z	=	High impedance ªoffº state

↑= Low-to-High clock transition

↑= Not a Low-to-High clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL	PARAMETER	RATING	UNIT
VCC	Supply voltage	±0.5 to +7.0	V
VIN	Input voltage	±0.5 to +7.0	V
IIN	Input current	±30 to +5.0	mA
VOUT	Voltage applied to output in High output state	±0.5 to +VCC	V
IOUT	Current applied to output in Low output state	48	mA
Tamb	Operating free-air temperature range	0 to +70	°C
Tstg	Storage temperature	±65 to +150	°C

RECOMMENDED OPERATING CONDITIONS

	SYMBOL	PARAMETER		LIMITS		UNIT
			MIN	NOM	MAX
	VCC	Supply voltage	4.5	5.0	5.5	V
	VIH	High-level input voltage	2.0			V
	VIL	Low-level input voltage			0.8	V
	IIK	Input clamp current			±18	mA
	IOH	High-level output current			±3	mA
	IOL	Low-level output current			24	mA
	Tamb	Operating free-air temperature range	0		70	°C

1989 Oct 16

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