INTEGRATED CIRCUITS
74F543
Octal registered transceiver, non-inverting (3-State)
74F544
Octal registered transceiver, inverting (3-State)
Product specification |
1994 Dec 5 |
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors |
Product specification |
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Octal registered transceivers |
74F543, 74F544 |
74F543 Octal registered transceiver, non-inverting (3-State) 74F544 Octal registered transceiver, inverting 93-State)
FEATURES
•Combines74F245 and 74F373 type functions in one chip
•8-bit octal transceiver with D-type latch
•74F543 Non-inverting 74F544 Inverting
•Back-to-back registers for storage
•Separate controls for data flow in each direction
•A outputs sink 20mA and source 3mA
•B outputs sink 64mA and source 15mA
•3-State outputs for bus-oriented applications
•74F543 available in SSOP Type II package
DESCRIPTION
The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. While the 74F543 has non-inverting data path, the 74F544 inverts data in both directions. The A outputs are guaranteed to sink
24mA, while the B outputs are rated for 64mA.
FUNCTIONAL DESCRIPTION
The 74F543 and 74F544 contain two sets of eight D-type latches, with separate input and controls for each set. For data flow from A to
B, for example, the A-to-B Enable (EAB) input must be Low in order to enter data from A0 - A7 or take data from B0 - B7, as indicated in the Function Table. With EAB Low, a Low signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent Low-to-High transition for the LEAB signal puts the
A latches in the storage mode and their outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State
B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
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TYPICAL |
TYPICAL |
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PROPAGATION |
SUPPLY CURRENT |
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DELAY |
(TOTAL) |
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74F543 |
6.0ns |
80mA |
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74F544 |
6.5ns |
95mA |
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ORDERING INFORMATION
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COMMERCIAL RANGE |
DRAWING |
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DESCRIPTION |
VCC = 5V ±10%, |
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NUMBER |
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TA = 0°C to +70°C |
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24-pin plastic skinny DIP (300mil) |
N74F543N, |
SOT222±1 |
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N74F544N |
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24-pin plastic SOL |
N74F543D, |
SOT137-1 |
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N74F544D |
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24-pin plastic SSOP Type II |
74F543DB |
SOT340-1 |
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INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
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PINS |
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DESCRIPTION |
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74F(U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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A0 - A7 |
Port A, 3-State inputs |
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3.5/1.0 |
70μA/0.6mA |
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B0 - B7 |
Port B, 3-State inputs |
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3.5/1.0 |
70μA/0.6mA |
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A-to-B Output Enable input (Active Low) |
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1.0/1.0 |
20μA/0.6mA |
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OEAB |
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B-to-A Output Enable input (Active Low) |
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1.0/1.0 |
20μA/0.6mA |
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74F543 |
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OEBA |
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74F544 |
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A-to-B Enable input (Active Low) |
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1.0/2.0 |
20μA/1.2mA |
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EAB |
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B-to-A Enable input (Active Low) |
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1.0/2.0 |
20μA/1.2mA |
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EBA |
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A-to-B Latch Enable input (Active Low) |
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1.0/1.0 |
20μA/0.6mA |
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LEAB |
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B-to-A Latch Enable input (Active Low) |
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1.0/1.0 |
20μA/0.6mA |
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LEBA |
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74F543 |
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A0 - A7 |
Port A, 3-State outputs |
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150/40 |
3.0mA/24mA |
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B0 - B7 |
Port B, 3-State outputs |
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750/106.7 |
15mA/64mA |
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Port |
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150/40 |
3.0mA/24mA |
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74F544 |
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A0 - A7 |
A, 3-State outputs |
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Port |
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750/106.7 |
15mA/64mA |
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B0 - B7 |
B, 3-State outputs |
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NOTE: One (1.0) FAST Unit Load is defined as: 20μA in the High State and 0.6mA in the Low state. |
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1994 Dec 5 |
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2 |
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853-0874 14379 |
Philips Semiconductors |
Product specification |
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Octal registered transceivers |
74F543, 74F544 |
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PIN CONFIGURATION ± 74F543 |
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LOGIC SYMBOL ± 74F543 |
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LEBA |
1 |
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24 |
VCC |
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3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
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OEBA |
2 |
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23 |
EBA |
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A0 |
3 |
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22 |
B0 |
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4 |
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21 |
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A0 A1 A2 A3 A4 A5 A6 A7 |
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A1 |
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B1 |
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A2 |
5 |
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20 |
B2 |
11 |
EAB |
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13 |
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6 |
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19 |
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23 |
EBA |
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OEAB |
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A3 |
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B3 |
14 |
LEAB |
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OEBA |
2 |
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A4 |
7 |
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18 |
B4 |
1 |
LEBA |
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A5 |
8 |
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17 |
B5 |
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A6 |
9 |
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16 |
B6 |
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B0 B1 B2 B3 B4 B5 B6 B7 |
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A7 |
10 |
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15 |
B7 |
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EAB |
11 |
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14 |
LEAB |
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22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
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GND |
12 |
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13 |
OEAB |
VCC = Pin 24 |
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GND = Pin 12 |
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SF00237 |
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SF00238 |
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LOGIC SYMBOL (IEEE/IEC) ± 74F543 |
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IEN3 |
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23 |
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G1 |
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1 |
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1C5 |
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13 |
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2EN4 |
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11 |
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G2 |
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14 |
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2C6 |
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3 |
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5D |
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6D |
4 |
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8 |
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SF00239 |
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1994 Dec 5 |
3 |
Philips Semiconductors |
Product specification |
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Octal registered transceivers |
74F543, 74F544 |
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PIN CONFIGURATION ± 74F544 |
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LOGIC SYMBOL ± 74F544 |
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LEBA |
1 |
24 |
VCC |
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3 |
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10 |
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OEBA |
2 |
23 |
EBA |
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A0 |
3 |
22 |
B0 |
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A1 |
4 |
21 |
B1 |
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A0 A1 A2 A3 A4 A5 A6 A7 |
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A2 |
5 |
20 |
B2 |
11 |
EAB |
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13 |
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A3 |
6 |
19 |
B3 |
23 |
EBA |
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OEAB |
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14 |
LEAB |
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OEBA |
2 |
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A4 |
7 |
18 |
B4 |
1 |
LEBA |
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A5 |
8 |
17 |
B5 |
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A6 |
9 |
16 |
B6 |
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B0 B1 B2 B3 B4 B5 B6 B7 |
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A7 |
10 |
15 |
B7 |
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EAB |
11 |
14 |
LEAB |
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GND |
12 |
13 |
OEAB |
VCC = Pin 24 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
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GND = Pin 12 |
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SF00240 |
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SF00242 |
LOGIC SYMBOL (IEEE/IEC) ± 74F544
2 |
IEN3 |
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23 |
G1 |
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1 |
1C5 |
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2EN4 |
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11 |
G2 |
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14 |
2C6 |
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3 |
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5D |
22 |
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4 |
6D |
4 |
21 |
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5 |
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20 |
6 |
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19 |
7 |
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18 |
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17 |
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16 |
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SF00241 |
FUNCTION TABLE for 74F543 and 74F544
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INPUTS |
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OUTPUTS |
STATUS |
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DATA |
74F543 |
74F544 |
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OEXX |
EXX |
LEXX |
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H |
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X |
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X |
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X |
Z |
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Z |
Disabled |
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X |
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H |
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X |
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X |
Z |
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Z |
Disabled |
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L |
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↑ |
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L |
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h |
Z |
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Z |
Disable + |
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L |
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↑ |
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L |
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l |
Z |
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Z |
Latch |
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L |
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L |
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↑ |
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h |
H |
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L |
Latch + |
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L |
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L |
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↑ |
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l |
L |
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H |
Display |
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L |
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L |
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L |
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H |
H |
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L |
Transparent |
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L |
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L |
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L |
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L |
L |
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H |
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L |
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L |
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H |
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X |
NC |
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NC |
Hold |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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h |
= |
High state must be present one setup time before the |
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Low-to-High transition of |
LEXX |
or |
EXX |
(XX=AB or BA) |
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l |
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Low state must be present one setup time before the |
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↑ |
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Low-to-High transition of |
LEXX |
or |
EXX |
(XX=AB or BA) |
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Low-to-High transition of |
LEXX |
or |
EXX |
XX = AB or BA |
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X |
= |
Don't care |
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NC = |
No change |
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Z |
= |
High impedance ªoffº state |
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1994 Dec 5 |
4 |
Philips Semiconductors |
Product specification |
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Octal registered transceivers |
74F543, 74F544 |
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LOGIC DIAGRAM FOR 74F543
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D |
Q |
DETAIL A |
22 |
B0 |
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LE |
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A0 |
3 |
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Q |
D |
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LE |
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A1 |
4 |
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21 |
B1 |
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A2 |
5 |
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20 |
B2 |
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A3 |
6 |
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19 |
B3 |
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A4 |
7 |
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DETAIL A X 7 |
18 |
B4 |
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A5 |
8 |
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17 |
B5 |
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A6 |
9 |
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16 |
B6 |
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A7 |
10 |
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15 |
B7 |
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OEBA |
2 |
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13 |
OEAB |
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EBA |
23 |
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11 |
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1 |
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EAB |
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LEBA |
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VCC = Pin 24 |
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14 |
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LEAB |
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GND = Pin 12 |
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SF00243 |
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LOGIC DIAGRAM FOR 74F544 |
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D |
DETAIL A |
22 |
B0 |
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Q |
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LE |
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A0 |
3 |
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Q |
D |
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LE |
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A1 |
4 |
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21 |
B1 |
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A2 |
5 |
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20 |
B2 |
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A3 |
6 |
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19 |
B3 |
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A4 |
7 |
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DETAIL A X 7 |
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18 |
B4 |
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A5 |
8 |
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17 |
B5 |
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9 |
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16 |
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A6 |
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B6 |
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10 |
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15 |
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A7 |
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B7 |
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OEBA |
2 |
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13 |
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OEAB |
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EBA |
23 |
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11 |
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1 |
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EAB |
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VCC = Pin 24 |
LEBA |
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14 |
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GND = Pin 12 |
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LEAB |
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SF00244 |
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1994 Dec 5 |
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5 |
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