RF COMMUNICATIONS PRODUCTS
OUTPUT/INPUT
INPUT/OUTPUT
OUTPUT/INPUT
ENCH1
SA630
Single pole double throw (SPDT) switch
Product Specification
1997 Nov 07
Replaces data of October 10, 1991 IC17 Data Handbook
Philips Semiconductors
Philips Semiconductors |
Product specification |
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Single pole double throw (SPDT) switch |
SA630 |
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DESCRIPTION
The SA630 is a wideband RF switch fabricated in BiCMOS technology and incorporating on-chip CMOS/TTL compatible drivers. Its primary function is to switch signals in the frequency range DC - 1GHz from one 50Ω channel to another. The switch is activated by a CMOS/TTL compatible signal applied to the enable channel 1 pin (ENCH1).
The extremely low current consumption makes the SA630 ideal for portable applications. The excellent isolation and low loss makes this a suitable replacement for PIN diodes.
The SA630 is available in an 8-pin dual in-line plastic package and an 8-pin SO (surface mounted miniature) package.
FEATURES
•Wideband (DC - 1GHz)
•Low through loss (1dB typical at 200MHz)
•Unused input is terminated internally in 50Ω
•Excellent overload capability (1dB gain compression point +18dBm at 300MHz)
•Low DC power (170μA from 5V supply)
•Fast switching (20ns typical)
•Good isolation (off channel isolation 60dB at 100MHz)
PIN CONFIGURATION
D and N Packages
VDD |
1 |
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8 |
OUT1 |
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GND |
2 |
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7 |
AC GND |
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INPUT |
3 |
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6 |
GND |
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ENCH1 |
4 |
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5 |
OUT2 |
SR00578
Figure 1. Pin Configuration
•Low distortion (IP3 intercept +33dBm)
•Good 50Ω match (return loss 18dB at 400MHz)
•Full ESD protection
•Bidirectional operation
APPLICATIONS
•Digital transceiver front-end switch
•Antenna switch
•Filter selection
•Video switch
•FSK transmitter
ORDERING INFORMATION
DESCRIPTION |
TEMPERATURE RANGE |
ORDER CODE |
DWG # |
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8-Pin Plastic Dual In-Line Package (DIP) |
-40 to +85°C |
SA630N |
SOT97-1 |
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8-Pin Plastic Small Outline (SO) package (Surface-mount) |
-40 to +85°C |
SA630D |
SOT96-1 |
BLOCK DIAGRAM
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INPUT/OUTPUT |
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OUTPUT/INPUT |
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OUTPUT/INPUT |
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ENCH1 |
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SR00579 |
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Figure 2. Block Diagram |
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RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
PARAMETER |
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RATING |
UNITS |
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VDD |
Supply voltage |
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3.0 to 5.5V |
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TA |
Operating ambient temperature range |
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-40 to +85 |
°C |
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SA Grade |
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TJ |
Operating junction temperature range |
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-40 to +105 |
°C |
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SA Grade |
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1997 Nov 07 |
2 |
853-1577 18666 |
Philips Semiconductors |
Product specification |
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Single pole double throw (SPDT) switch |
SA630 |
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EQUIVALENT CIRCUIT |
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VDD |
1 |
8 |
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+5V |
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OUT1 |
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20kΩ |
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CONTROL |
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LOGIC |
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50Ω |
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7 |
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2 |
AC BYPASS |
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50Ω |
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6 |
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INPUT |
3 |
20kΩ |
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4 |
OUT2 |
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ENCH1 |
5 |
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SR00580 |
Figure 3. Equivalent Circuit
ABSOLUTE MAXIMUM RATINGS
SYMBOL |
PARAMETER |
RATING |
UNITS |
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VDD |
Supply voltage |
-0.5 to +5.5 |
V |
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Power dissipation, T = 25oC (still air)1 |
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A |
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PD |
8-Pin Plastic DIP |
1160 |
mW |
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8-Pin Plastic SO |
780 |
mW |
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TJMAX |
Maximum operating junction temperature |
150 |
°C |
PMAX |
Maximum power input/output |
+20 |
dBm |
TSTG |
Storage temperature range |
-65 to +150 |
°C |
NOTES:
1. Maximum dissipation is determined by the operating ambient temperature and the thermal resistance, θJA: 8-Pin DIP: θJA = 108°C/W
8-Pin SO: θJA = 158°C/W
DC ELECTRICAL CHARACTERISTICS
VDD = +5V, TA = 25°C; unless otherwise stated.
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LIMITS |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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SA630 |
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UNITS |
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MIN |
TYP |
MAX |
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IDD |
Supply current |
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40 |
170 |
300 |
μA |
V |
TTL/CMOS logic threshold voltage1 |
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1.1 |
1.25 |
1.4 |
V |
T |
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VIH |
Logic 1 level |
Enable channel 1 |
2.0 |
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VDD |
V |
VIL |
Logic 0 level |
Enable channel 2 |
-0.3 |
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0.8 |
V |
IIL |
ENCH1 input current |
ENCH1 = 0.4V |
-1 |
0 |
1 |
μA |
IIH |
ENCH1 input current |
ENCH1 = 2.4V |
-1 |
0 |
1 |
μA |
NOTE:
1. The ENCH1 input must be connected to a valid Logic Level for proper operation of the SA630.
1997 Nov 07 |
3 |
Philips Semiconductors |
Product specification |
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Single pole double throw (SPDT) switch |
SA630 |
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AC ELECTRICAL CHARACTERISTICS1 - D PACKAGE
VDD = +5V, |
TA = 25°C; unless otherwise stated. |
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LIMITS |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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SA630 |
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UNITS |
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MIN |
TYP |
MAX |
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DC - 100MHz |
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1 |
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S21, S12 |
Insertion loss (ON channel) |
500MHz |
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1.4 |
2.8 |
dB |
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900MHz |
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2 |
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10MHz |
70 |
80 |
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S |
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12 |
Isolation (OFF channel)2 |
100MHz |
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60 |
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dB |
21 |
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500MHz |
24 |
50 |
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900MHz |
30 |
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S11, S22 |
Return loss (ON channel) |
DC - 400MHz |
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20 |
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dB |
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900MHz |
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12 |
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S11, S22 |
Return loss (OFF channel) |
DC - 400MHz |
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17 |
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dB |
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900MHz |
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13 |
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tD |
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Switching speed (on-off delay) |
50% TTL to 90/10% RF |
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20 |
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tr, tf |
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Switching speeds (on-off rise/fall time) |
90%/10% to 10%/90% RF |
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5 |
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ns |
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Switching transients |
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165 |
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mVP-P |
P-1dB |
1dB gain compression |
DC - 1GHz |
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+18 |
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dBm |
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IP3 |
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Third-order intermodulation intercept |
100MHz |
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+33 |
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dBm |
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IP2 |
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Second-order intermodulation intercept |
100MHz |
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+52 |
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dBm |
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NF |
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Noise figure (ZO = 50Ω ) |
100MHz |
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1.0 |
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dB |
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900MHz |
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2.0 |
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NOTE:
1.All measurements include the effects of the D package SA630 Evaluation Board (see Figure 4B). Measurement system impedance is 50Ω.
2.The placement of the AC bypass capacitor is critical to achieve these specifications. See the applications section for more details.
AC ELECTRICAL CHARACTERISTICS1 - N PACKAGE
VDD = +5V, TA = 25°C; all other characteristics similar to the D-Package, unless otherwise stated.
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LIMITS |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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SA630 |
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UNITS |
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MIN |
TYP |
MAX |
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DC - 100MHz |
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1 |
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S21, S12 |
Insertion loss (ON channel) |
500MHz |
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1.4 |
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dB |
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900MHz |
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2.5 |
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10MHz |
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68 |
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S21, S12 |
Isolation (OFF channel) |
100MHz |
58 |
50 |
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dB |
500MHz |
37 |
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900MHz |
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15 |
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NF |
Noise figure (ZO = 50Ω ) |
100MHz |
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1.0 |
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dB |
900MHz |
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2.5 |
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NOTE:
1. All measurements include the effects of the N package SA630 Evaluation Board (see Figure 4C). Measurement system impedance is 50Ω.
APPLICATIONS
The typical applications schematic and printed circuit board layout of the SA630 evaluation board is shown in Figure 4. The layout of the board is simple, but a few cautions need to be observed. The input and output traces should be 50Ω. The placement of the AC bypass capacitor is extremely critical if a symmetric isolation between the two channels is desired. The trace from Pin 7 should be drawn back towards the package and then be routed downwards. The capacitor
should be placed straight down as close to the device as practical. For better isolation between the two channels at higher frequencies, it is also advisable to run the two output/input traces at an angle. This also minimizes any inductive coupling between the two traces. The power supply bypass capacitor should be placed close to the device. Figure 10 shows the frequency response of the SA630. The loss matching between the two channels is excellent to 1.2GHz as shown in Figure 13.
1997 Nov 07 |
4 |
Philips Semiconductors |
Product specification |
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Single pole double throw (SPDT) switch |
SA630 |
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VDD |
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+5V |
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D and N Packages |
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0.1μF |
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0.01μF |
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1 |
8 |
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OUT1 |
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GND |
7 |
AC GND |
0.01μF |
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2 |
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INPUT |
3 |
6 |
GND |
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0.01μF |
5 |
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4 |
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OUT2 |
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ENCH1 |
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0.01μF |
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a. Evaluation Board Schematic |
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b. 630 D-Package Board Layout |
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630N1 |
7/91 |
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c. 630 N-Package Board Layout |
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SR00581 |
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Figure 4. Board and Package Graphics
1997 Nov 07 |
5 |
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