Philips N74F821D, N74F821N, N74F822D, N74F822N, N74F823D Datasheet

INTEGRATED CIRCUITS

74F821/822/823/824/825/826

Bus interface registers

Product specification

1996 Jan 05

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
Bus interface registers	74F821/822/823/824/825/826

74F821 10-bit bus interface register, non-inverting (3-State) 74F822 10-bit bus interface register, inverting (3-State) 74F823 9-bit bus interface register, non-inverting (3-State) 74F824 9-bit bus interface register, inverting (3-State) 74F825 8-bit bus interface register, non-inverting (3-State) 74F826 8-bit bus interface register, inverting (3-State)

FEATURES

•High speed parallel registers with positive edge-triggered D-type flip-flops

•High performance bus interface buffering for wide data/address paths or busses carrying parity

•High impedance PNP base inputs for reduced loading (20μA in high and low states)

•IIL is 20μA vs 1000μA for AM29821 series

•Buffered control inputs to reduce AC effects

•Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor

•Positive and negative over-shoots are clamped to ground

•3-State outputs glitch free during power-up and power-down

•Slim Dip 300 mil package

•Broadside pinout compatible with AMD AM 29821-29826 series

•Outputs sink 64mA and source 24mA

•Industrial temperature range available (±40°C to +85°C) for 74F823

DESCRIPTION

The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity.

The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions.

The 74F822 is the inverted output version of 74F821.

The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems.

The 74F824 is the inverted version of 74F823.

The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. They are ideal for uses as an output port requiring high IOL/IOH.

The 74F826 is the inverted version of 74F825.

		TYPICAL	TYPICAL
	TYPE		SUPPLY CURRENT
		fmax
			(TOTAL)
	74F821, 74F822	180MHz	75mA
	74F823, 74F824	180MHz	70mA
	74F825, 74F826	180MHz	65mA

ORDERING INFORMATION

	ORDER CODE
DESCRIPTION	COMMERCIAL RANGE		INDUSTRIAL RANGE	PKG. DWG. #
	VCC = 5V ±10%,		VCC = 5V ±10%,
	Tamb = 0°C to +70°C		Tamb = ±40°C to +85°C
24-pin plastic slim DIP (300mil)	N74F821N, N74F822N, N74F823N,		I74F823N	SOT222-1
	N74F824N, N74F825N, N74F826N
24-pin plastic SOL	N74F821D, N74F822D, N74F823D,		I74F823D	SOT137-1
	N74F824D, N74F825D, N74F826D

1996 Jan 05

2

853-1304 16195

Philips Semiconductors	Product specification
Bus interface registers	74F821/822/823/824/825/826

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

LOAD VALUE

HIGH/LOW

HIGH/LOW

Dn

Data inputs

1.0/1.0

20μA/0.6mA

74F821

CP

Clock input

1.0/1.0

20μA/0.6mA

74F822

Output enable input (active low)

1.0/3.0

20μA/1.8mA

OE

Qn,

Data outputs

1200/106.7

24mA/64mA

Qn

Dn

Data inputs

1.0/1.0

20μA/0.6mA

CP

Clock input

1.0/1.0

20μA/0.6mA

74F823

Clock enable input (active low)

1.0/3.0

20μA/1.8mA

CE

74F824

Master reset input (active low)

1.0/3.0

20μA/1.8mA

MR

Output enable input (active low)

1.0/3.0

20μA/1.8mA

OE

Qn,

Data outputs

1200/106.7

24mA/64mA

Qn

Dn

Data inputs

1.0/1.0

20μA/0.6mA

CP

Clock input

1.0/1.0

20μA/0.6mA

74F825

Clock enable input (active low)

1.0/3.0

20μA/1.8mA

CE

74F826

Master reset input (active low)

1.0/3.0

20μA/1.8mA

MR

Output enable input (active low)

1.0/3.0

20μA/1.8mA

OE

Qn,

Data outputs

1200/106.7

24mA/64mA

Qn

NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

PIN CONFIGURATION ± 74F821											LOGIC SYMBOL ± 74F821
													2		3		4		5		6		7		8		9		10		11
	OE			1				24	VCC
	D0			2				23	Q0
													D0		D1		D2		D3		D4		D5		D6		D7		D8		D9
	D1			3				22	Q1
	D2			4				21	Q2
											13		CP
	D3			5				20	Q3
											1		OE
	D4			6				19	Q4
	D5			7				18	Q5
													Q0		Q1		Q2		Q3		Q4		Q5		Q6		Q7		Q8		Q9
	D6			8				17	Q6
	D7			9				16	Q7
													23		22		21		20		19		18		17		16		15		14
	D8			10				15	Q8		VCC = Pin 24
	D9								Q9		GND = Pin 12																		SF00483
				11				14
GND
			12					13	CP
							SF00482

1996 Jan 05

3

Philips Semiconductors	Product specification
Bus interface registers	74F821/822/823/824/825/826

IEC/IEEE SYMBOL ± 74F821									IEC/IEEE SYMBOL ± 74F822
1									1
											EN1
		EN1
									13
13											G2
		G2
									2						23
2						23					2D		1
		2D		1					3						22
3						22
									4						21
4						21
									5						20
5						20
									6						19
6						19
									7						18
7						18
									8						17
8						17
									9						16
9						16
									10						15
10						15
									11						14
11						14
							SF00484								SF00487

PIN CONFIGURATION ± 74F822

OE			1				24		VCC
	D0		2				23		Q0
	D1		3				22		Q1
	D2		4				21		Q2
	D3		5				20		Q3
	D4		6				19		Q4
	D5		7				18		Q5
	D6		8				17		Q6
	D7		9				16		Q7
	D8		10				15		Q8
	D9
			11				14		Q9
GND
		12					13		CP
						SF00485

LOGIC SYMBOL ± 74F822

	2	3	4	5	6	7	8	9	10	11
	D0	D1	D2	D3	D4	D5	D6	D7	D8	D9
13	CP
1	OE
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7	Q8	Q9
	23	22	21	20	19	18	17	16	15	14

VCC = Pin 24
GND = Pin 12	SF00486

PIN CONFIGURATION ± 74F823

	OE			1				24		VCC
	D0			2				23		Q0
	D1			3				22		Q1
	D2			4				21		Q2
	D3			5				20		Q3
	D4			6				19		Q4
	D5									Q5
				7				18
	D6			8				17		Q6
	D7			9				16		Q7
	D8			10				15		Q8
	MR			11				14		CE
GND
			12					13		CP
							SF00488

LOGIC SYMBOL ± 74F823

2

3

4

5

6

7

8

9

10

D0 D1 D2 D3 D4 D5 D6 D7 D8

13CP

14 CE

11 MR

1 OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

23 22 21 20 19 18 17 16 15

VCC = Pin 24

GND = Pin 12

SF00489

1996 Jan 05

4

Philips Semiconductors	Product specification
Bus interface registers	74F821/822/823/824/825/826

IEC/IEEE SYMBOL ± 74F823								IEC/IEEE SYMBOL ± 74F824
1								1
		EN1								EN1
								11
11		R								R
									14
14		G1								G1
									13
	13		1G2								1G2
								2						23
2						23
		2D		1						2D		1
								3						22
3						22
4						21		4						21
5						20		5						20
6						19		6						19
7						18		7						18
8						17		8						17
9						16		9						16
10						15		10						15
						SF00490								SF00493

PIN CONFIGURATION ± 74F824

	OE			1				24	VCC
	D0			2				23
										Q0
	D1			3				22		Q1
	D2			4				21		Q2
	D3			5				20		Q3
	D4			6				19		Q4
	D5
				7				18		Q5
	D6			8				17		Q6
	D7			9				16		Q7
	D8			10				15		Q8
	MR			11				14		CE
GND
			12					13	CP
							SF00491

LOGIC SYMBOL ± 74F824

2

3

4

5

6

7

8

9

10

D0 D1 D2 D3 D4 D5 D6 D7 D8

13	CP
14	CE
11	MR
1	OE
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7	Q8
	23	22	21	20	19	18	17	16	15

VCC = Pin 24
GND = Pin 12	SF00492

PIN CONFIGURATION ± 74F825

	OE0						1				24		VCC
		OEI					2				23		OE2
		DO					3				22	QO
		D1					4				21	Q1
		D2					5				20	Q2
												Q3
		D3					6				19
												Q4
		D4					7				18
		D5										Q5
							8				17
		D6										Q6
							9				16
												Q7
		D7					10				15
		MR					11				14		CE
GND												CP
						12					13
										SF00494

LOGIC SYMBOL ± 74F825

3

4

5

6

7

8

9

10

D0 D1 D2 D3 D4 D5 D6 D7

13CP

14 CE

11 MR

1 OE0

2 OE1

23 OE2

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

22 21 20 19 18 17 16 15

VCC = Pin 24

GND = Pin 12

SF00495

1996 Jan 05

5

Philips Semiconductors	Product specification
Bus interface registers	74F821/822/823/824/825/826

IEC/IEEE SYMBOL ± 74F825

1&

2EN

	11	R
	14	G1
	13
		1G2

3					22
	2D		1
4					21
5					20
6					19
7					18
8					17
9					16
10					15

SF00496

PIN CONFIGURATION ± 74F826

	OE0						1				24		VCC
		OEI					2				23		OE2
		DO					3				22	QO
		D1					4				21	Q1
		D2					5				20	Q2
												Q3
		D3					6				19
												Q4
		D4					7				18
		D5										Q5
							8				17
		D6										Q6
							9				16
												Q7
		D7					10				15
		MR					11				14		CE
GND												CP
						12					13
										SF00497

LOGIC DIAGRAM FOR 74F821

LOGIC SYMBOL ± 74F826

3

4

5

6

7

8

9

10

D0 D1 D2 D3 D4 D5 D6 D7

13CP

14 CE

11 MR

1 OE0

2 OE1

23 OE2

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

22 21 20 19 18 17 16 15

VCC = Pin 24

GND = Pin 12

SF00498

IEC/IEEE SYMBOL ± 74F826

1&

2EN

	11	R
	14	G1
	13
		1G2

3					22
	2D		1
4					21
5					20
6					19
7					18
8					17
9					16
10					15

SF00499

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

2

3

4

5

6

7

8

9

10

11

D

D

D

D

D

D

D

D

D

D

CP Q

CP Q

CP Q

CP Q

CP Q

CP Q

CP Q

CP Q

CP Q

CP Q

CP

13

OE

1

23

22

21

20

19

18

17

16

15

14

VCC = Pin 24

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

GND = Pin 12

SF00500

1996 Jan 05

6