Philips N74F843N, N74F844D, N74F844N, N74F843D, N74F842D Datasheet

INTEGRATED CIRCUITS

74F841/842/843/845/846

Bus interface latches

Product specification

1999 Jun 23

Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08

IC15 Data Handbook

P s

on o s

	Philips Semiconductors	Product specification
	Bus interface latches	74F841/74F842/74F843/
		74F845/74F846

74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 74F843 9-bit bus interface latch, non-inverting (3-State)

74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)

FEATURES

•High speed parallel latches

•Extra data width for wide address/data paths or buses carrying parity

•High impedance NPN base input structure minimizes bus loading

•IIL is 20μA vs 1000A for AM29841 series

•Buffered control inputs to reduce AC effects

•Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors

•Positive and negative over-shoots are clamped to ground

•3-State outputs glitch free during power-up and power-down

•48mA sink current

•Slim dual in-line 300 mil package

•Broadside pinout

•Pin-for-pin and function compatible with AMD AM29841-846 series

	TYPICAL	TYPICAL
TYPE	PROPAGATION	SUPPLY CURRENT
	DELAY	(TOTAL)
74F841, 74F842	5.5ns	60mA
74F843, 74F845	5.5ns	75mA
74F846	6.2ns	60mA

DESCRIPTION

The 74F841±74F846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity.

The 74F841±74F846 series are funcitonally an pin compatible to the AMD AM29841±AM29846 series.

The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched.

Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state.

The 74F842 is the inverted output version of the 74F841.

The 74F843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, the 74F843 has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low, PRE overrides MR.

The 74F845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74F845 has two addtitional OE pins making a total of three Output Enables (OE0, OE1, OE2) pins.

The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user control of the interface, e.g., CS, DMA, and RD/WR.

The 74F846 is the inverted output version of the 74F845.

ORDERING INFORMATION

	PACKAGES	COMMERCIAL RANGE	PACKAGE DRAWING
		VCC = 5V±10%; Tamb = 0°C to +70°C	NUMBER
	24-pin plastic Slim DIP (300 mil)	N74F841N, N74F842N, N74F843N, N74F845N, N74F846N	SOT222-1
	24-pin plastic SOL	N74F841D, N74F842D, N74F843D, N74F845D, N74F846D	SOT137-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

LOAD VALUE

HIGH/LOW

HIGH/LOW

Dn

Data inputs

1.0/0.033

20μA/20μA

LE

Latch Enable input

1.0/0.033

20μA/20μA

Output Enable input (active Low)

1.0/0.033

20μA/20μA

OE,

OEn

Master Reset input (active Low)

1.0/0.033

20μA/20μA

MR

Preset input (active Low)

1.0/0.033

20μA/20μA

PRE

Qn

Data outputs

1200/80

24mA/48mA

Data outputs

1200/80

24mA/48mA

Qn

NOTE: One (1.0) FAST Unit Load is defined as: 20μA in the High state and 0.6mA in the Low state.

1999 Jun 23

2

853±1208 21851

Philips Semiconductors	Product specification

Bus interface latches

74F841/74F842/74F843/

74F845/74F846

PIN CONFIGURATION for 74F841

		1	24	VCC
	OE
	D0	2	23	Q0
	D1	3	22	Q1
	D2	4	21	Q2
	D3	5	20	Q3
	D4	6	19	Q4
	D5	7	18	Q5
	D6	8	17	Q6
	D7	9	16	Q7
	D8	10	15	Q8
	D9	11	14	Q9
GND		12	13	LE
			SF01279

PIN CONFIGURATION for 74F842

		1	24	VCC
	OE
	D0	2	23
					Q0
	D1	3	22
				Q1
	D2	4	21
				Q2
	D3	5	20
				Q3
	D4	6	19
				Q4
	D5	7	18
				Q5
	D6	8	17
				Q6
	D7	9	16
				Q7
	D8	10	15
				Q8
	D9	11	14
				Q9
GND		12	13	LE
			SF01282

LOGIC SYMBOL for 74F841

	2			3		4		5		6		7		8		9		10		11
		D0		D1		D2		D3		D4		D5		D6		D7		D8		D9
13		LE
1		OE
		Q0		Q1		Q2		Q3		Q4		Q5		Q6		Q7		Q8		Q9
	23			22		21		20		19		18		17		16		15		14

VCC = Pin 24
GND = Pin 12	SF01280

LOGIC SYMBOL for 74F842

	2	3	4	5	6	7	8	9	10	11
	D0	D1	D2	D3	D4	D5	D6	D7	D8	D9
13	LE
1	OE
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7	Q8	Q9
	23	22	21	20	19	18	17	16	15	14

VCC = Pin 24
GND = Pin 12	SF01283

LOGIC SYMBOL (IEEE/IEC) for 74F841												LOGIC SYMBOL (IEEE/IEC) for 74F842
	1												1
																EN
				EN								13
13																C1
				C1
		2						23						2						23
																1 D
				1 D
														3						22
		3						22
														4						21
		4						21
														5						20
		5						20
														6						19
		6						19
														7						18
		7						18
														8						17
		8						17
														9						16
		9						16
														10						15
		10					15
														11					14
		11					14
								SF01281
																			SF01284

1999 Jun 23

3

Philips Semiconductors	Product specification

Bus interface latches

74F841/74F842/74F843/

74F845/74F846

PIN CONFIGURATION for 74F843

		OE		1	24	VCC
		D0		2	23	Q0
		D1		3	22	Q1
		D2		4	21	Q2
		D3		5	20	Q3
		D4		6	19	Q4
		D5		7	18	Q5
		D6		8	17	Q6
		D7		9	16	Q7
		D8		10	15	Q8
				11	14
	MR					PRE
GND				12	13	LE

SF01285

LOGIC SYMBOL for 74F843

	2			3		4		5		6		7		8		9		10
		D0		D1		D2		D3		D4		D5		D6		D7		D8
13		LE
14		PRE
11		MR
1		OE		Q1		Q2		Q3		Q4		Q5		Q6		Q7		Q8
		Q0
	23			22		21		20		19		18		17		16		15

VCC = Pin 24
GND = Pin 12	SF01286

LOGIC SYMBOL (IEEE/IEC) for 74F843

1

EN

11

R

14

S2

13

C1

	2					23
		1 D
	3				22
	4				21
	5				20
	6				19
	7				18
	8				17
	9				16
	10				15
					SF01287

1999 Jun 23

4

Philips Semiconductors	Product specification

Bus interface latches

74F841/74F842/74F843/

74F845/74F846

PIN CONFIGURATION for 74F845												PIN CONFIGURATION for 74F846
						1	24	VCC											1	24	VCC
	OE0													OE0
						2	23												2	23
	OE1							OE2					OE1									OE2
		D0				3	22	Q0							D0				3	22
																						Q0
		D1				4	21	Q1							D1				4	21
																					Q1
		D2				5	20	Q2							D2				5	20
																					Q2
		D3				6	19	Q3							D3				6	19
																					Q3
		D4				7	18	Q4							D4				7	18
																					Q4
		D5				8	17	Q5							D5				8	17
																					Q5
		D6				9	16	Q6							D6				9	16
																					Q6
		D7				10	15	Q7							D7				10	15
																					Q7
						11	14												11	14
		MR						PRE							MR							PRE
GND						12	13	LE				GND							12	13	LE
							SF01291													SF01294

LOGIC SYMBOL for 74F845

		3		4		5		6		7		8		9		10
		D0		D1		D2		D3		D4		D5		D6		D7
13		LE
14		PRE
11		MR
1		OE0
2		OE1
23		OE2
		Q0		Q1		Q2		Q3		Q4		Q5		Q6		Q7
VCC = Pin 24
		22		21		20		19		18		17		16		15
GND = Pin 12

SF01292

LOGIC SYMBOL for 74F846

3

4

5

6

7

8

9

10

D0 D1 D2 D3 D4 D5 D6 D7

13LE

14 PRE

11 MR

1 OE0

2 OE1

23 OE2

	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
VCC = Pin 24	22	21	20	19	18	17	16	15
GND = Pin 12

SF01295

LOGIC SYMBOL (IEEE/IEC) for 74F845												LOGIC SYMBOL (IEEE/IEC) for 74F846
1												1
	2			&											&
													2
					EN											EN
23
												23
14				S2								14			S2
	11
												11
				R
13															R
												13
				C1
															C1
3								22				3								22
				1 D											1 D
		4						21				4							21
		5						20
												5							20
		6						19
												6							19
		7						18
												7							18
		8						17
												8							17
		9						16
												9							16
		10						15
												10
																		15
						SF01293A											SF01296A

1999 Jun 23

5

Philips Semiconductors	Product specification

Bus interface latches

74F841/74F842/74F843/

74F845/74F846

LOGIC DIAGRAM for 74F841

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

2

3

4

5

6

7

8

9

10

11

D

D

D

D

D

D

D

D

D

D

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

C

LE

13

OE

1

23

22

21

20

19

18

17

16

15

14

VCC = Pin 24

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

GND = Pin 12

SF01297

LOGIC DIAGRAM for 74F842

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

2

3

4

5

6

7

8

9

10

11

D

D

D

D

D

D

D

D

D

D

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

L

Q

C

LE

13

OE

1

23

22

21

20

19

18

17

16

15

14

VCC = Pin 24

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

GND = Pin 12

SF01298

FUNCTION TABLE for 74F841 and 74F842

INPUTS

OUTPUTS

74F841

74F842

OPERATING MODE

LE

Dn

Qn

OE

Qn

L

H

L

L

H

Transparent

L

H

H

H

L

L

↓

l

L

H

Latched

L

↓

h

H

L

H

X

X

Z

Z

High Impedance

L

L

X

NC

NC

Hold

H

=

High voltage level

L

=

Low voltage level

h

=

High state one setup time before the High-to-Low LE transition

l

=

Low state one setup time before the High-to-Low LE transition

↓ =

High-to-Low transition

X

=

Don't care

NC=

No change

Z

=

High impedance ªoffº state

1999 Jun 23

6