Texas Instruments JM38510-65803BFA, JM38510-65803BEA, SN54HC139J, SN74HC139D, SN74HC139DR Datasheet
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SN54HC139, SN74HC139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS108B ± DECEMBER 1982 ± REVISED MAY 1997
D Designed Specifically for High-Speed |
SN54HC139 . . . J OR W PACKAGE |
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Memory Decoders and Data Transmission |
SN74HC139 . . . D, N, OR PW PACKAGE |
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Systems |
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D Incorporate Two Enable Inputs to Simplify |
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VCC |
1G |
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1 |
16 |
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Cascading and/or Data Reception |
1A |
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2 |
15 |
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2G |
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D Package Options Include Plastic |
1B |
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3 |
14 |
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2A |
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Small-Outline (D), Thin Shrink |
1Y0 |
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4 |
13 |
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2B |
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Small-Outline (PW), and Ceramic Flat (W) |
1Y1 |
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5 |
12 |
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2Y0 |
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Packages, Ceramic Chip Carriers (FK), and |
1Y2 |
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6 |
11 |
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2Y1 |
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Standard Plastic (N) and Ceramic (J) |
1Y3 |
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7 |
10 |
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2Y2 |
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300-mil DIPs |
GND |
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8 |
9 |
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2Y3 |
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description
The 'HC139 are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The 'HC139 comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
SN54HC139 . . . FK PACKAGE
(TOP VIEW)
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1A |
1G |
NC |
CC |
2G |
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V |
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1B |
3 |
2 |
1 |
20 19 |
2A |
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4 |
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18 |
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1Y0 |
5 |
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17 |
2B |
NC |
6 |
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16 |
NC |
1Y1 |
7 |
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15 |
2Y0 |
1Y2 |
8 |
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14 |
2Y1 |
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9 10 11 12 13 |
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1Y3 |
GND |
NC |
2Y3 |
2Y2 |
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NC ± No internal connection
The SN54HC139 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74HC139 is characterized for operation from ±40°C to 85°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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SELECT |
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G |
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B |
A |
Y0 |
Y1 |
Y2 |
Y3 |
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H |
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X |
X |
H |
H |
H |
H |
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L |
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L |
L |
L |
H |
H |
H |
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L |
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L |
H |
H |
L |
H |
H |
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L |
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H |
L |
H |
H |
L |
H |
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L |
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H |
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H |
H |
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L |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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SN54HC139, SN74HC139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS108B ± DECEMBER 1982 ± REVISED MAY 1997
logic symbols (alternatives)²
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X/Y |
4 |
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DMUX |
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4 |
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2 |
0 |
1Y0 |
2 |
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0 |
1Y0 |
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1A |
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1 |
5 |
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1A |
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0 |
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G |
0 |
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5 |
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3 |
1 |
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1Y1 |
3 |
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1 |
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1Y1 |
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6 |
1 |
3 |
6 |
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1B |
2 |
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1B |
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1 |
2 |
7 |
1Y2 |
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1 |
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2 |
7 |
1Y2 |
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1G |
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EN |
1Y3 |
1G |
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3 |
1Y3 |
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3 |
12 |
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12 |
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14 |
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2Y0 |
14 |
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2Y0 |
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2A |
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11 |
2Y1 |
2A |
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11 |
2Y1 |
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13 |
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13 |
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2B |
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10 |
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2B |
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10 |
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15 |
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2Y2 |
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15 |
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2Y2 |
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2G |
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9 |
2Y3 |
2G |
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9 |
2Y3 |
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² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic)
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4 |
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1Y0 |
1 |
5 |
1G |
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1Y1 |
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6 |
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1Y2 |
2 |
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1A |
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7 |
3 |
1Y3 |
1B |
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12 |
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2Y0 |
15 |
11 |
2G |
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2Y1 |
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10 |
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2Y2 |
14 |
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2A |
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13 |
9 |
2Y3 |
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2B |
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Pin numbers shown are for the D, J, N, PW, and W packages.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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