Texas Instruments JM38510-37101BCA, JM38510-37101B2A, SN54ALS74AJ, SN54AS74AJ, SN74ALS74AD Datasheet
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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C ± APRIL 1982 ± REVISED AUGUST 1995
• Package Options Include Plastic |
SN54ALS74A, SN54AS74A . . . J PACKAGE |
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Small-Outline (D) Packages, Ceramic Chip |
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE |
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Carriers (FK), and Standard Plastic (N) and |
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Ceramic (J) 300-mil DIPs |
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1CLR |
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1 |
14 |
VCC |
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1D |
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2 |
13 |
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2CLR |
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TYPICAL MAXIMUM |
TYPICAL POWER |
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1CLK |
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3 |
12 |
2D |
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TYPE |
CLOCK FREQUENCY |
DISSIPATION |
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(CL = 50 pF) |
PER FLIP-FLOP |
1PRE |
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4 |
11 |
2CLK |
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(MHz) |
(mW) |
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1Q |
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5 |
10 |
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2PRE |
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′ALS74A |
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2Q |
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50 |
6 |
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1Q |
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6 |
9 |
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GND |
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′AS74A |
134 |
26 |
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7 |
8 |
2Q |
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description
SN54ALS74A, SN54AS74A . . . FK PACKAGE
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
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(TOP VIEW) |
2CLR |
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1D |
1CLR |
NC |
V |
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CC |
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1CLK |
3 |
2 |
1 |
20 19 |
2D |
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4 |
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18 |
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NC |
5 |
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17 |
NC |
1PRE |
6 |
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16 |
2CLK |
NC |
7 |
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15 |
NC |
1Q |
8 |
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14 |
2PRE |
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9 |
10 11 12 13 |
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1Q |
GND |
NC |
2Q |
2Q |
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NC ± No internal connection |
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The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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CLK |
D |
Q |
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PRE |
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CLR |
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Q |
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L |
H |
X |
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H |
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L |
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H |
L |
X |
X |
L |
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H |
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L |
L |
X |
X |
H² |
H² |
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H |
H |
↑ |
H |
H |
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L |
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H |
H |
↑ |
L |
L |
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H |
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H |
H |
L |
X |
Q0 |
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Q |
0 |
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²The output levels in this configuration are not
specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C ± APRIL 1982 ± REVISED AUGUST 1995
logic symbol²
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4 |
S |
5 |
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1PRE |
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1Q |
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3 |
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C1 |
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1CLK |
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2 |
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1D |
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1D |
6 |
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1 |
R |
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1Q |
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1CLR |
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10 |
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9 |
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2PRE |
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2Q |
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11 |
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2CLK |
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12 |
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2D |
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8 |
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13 |
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2Q |
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2CLR |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
PRE
CLR |
Q |
Q
CLK
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . 7 V |
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . 7 V |
Operating free-air temperature range, TA: SN54ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±55°C to 125°C |
SN74ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 0°C to 70°C |
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±65°C to 150°C |
³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C ± APRIL 1982 ± REVISED AUGUST 1995
recommended operating conditions
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SN54ALS74A |
SN74ALS74A |
UNIT |
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MIN |
NOM |
MAX |
MIN |
NOM |
MAX |
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VCC |
Supply voltage |
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4.5 |
5 |
5.5 |
4.5 |
5 |
5.5 |
V |
VIH |
High-level input voltage |
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2 |
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2 |
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V |
VIL |
Low-level input voltage |
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0.7 |
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0.8 |
V |
IOH |
High-level output current |
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± 0.4 |
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± 0.4 |
mA |
IOL |
Low-level output current |
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4 |
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8 |
mA |
fclock |
Clock frequency |
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0 |
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25 |
0 |
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34 |
MHz |
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PRE |
or |
CLR |
low |
15 |
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15 |
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tw |
Pulse duration |
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ns |
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CLK high |
17.5 |
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14.5 |
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CLK low |
17.5 |
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14.5 |
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tsu |
Setup time before CLK↑ |
Data |
16 |
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15 |
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ns |
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PRE or CLR inactive |
10 |
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10 |
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th |
Hold time after CLK↑ |
Data |
2 |
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0 |
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ns |
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TA |
Operating free-air temperature |
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± 55 |
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125 |
0 |
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70 |
°C |
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
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PARAMETER |
TEST CONDITIONS |
SN54ALS74A |
SN74ALS74A |
UNIT |
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MIN TYP² |
MAX |
MIN TYP² |
MAX |
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VIK |
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VCC = 4.5 V, |
II = ±18 mA |
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±1.5 |
V |
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VOH |
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VCC = 4.5 V to 5.5 V, |
IOH = ± 2 mA |
VCC ± 2 |
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VCC ± 2 |
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V |
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VOL |
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VCC = 4.5 V |
IOL = 4 mA |
0.25 |
0.4 |
0.25 |
0.4 |
V |
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IOL = 8 mA |
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0.35 |
0.5 |
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II |
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CLK or D |
VCC = 4.5 V, |
VI = 7 V |
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0.1 |
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0.1 |
mA |
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PRE or CLR |
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0.2 |
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0.2 |
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IIH |
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CLK or D |
VCC = 4.5 V, |
VI = 2.7 V |
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20 |
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20 |
mA |
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PRE or CLR |
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40 |
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40 |
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IIL |
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CLK or D |
VCC = 4.5 V, |
VI = 0.4 V |
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± 0.2 |
mA |
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PRE or CLR |
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± 0.4 |
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± 0.4 |
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I |
³ |
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V = 5.5 V, |
V = 2.25 V |
± 20 |
±112 |
± 30 |
±112 |
mA |
O |
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CC |
O |
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ICC |
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VCC = 5.5 V, |
See Note 1 |
2.4 |
4 |
2.4 |
4 |
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² All typical values are at VCC = 5 V, TA = 25°C.
³The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
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