Texas Instruments JM38510-65352B2A, JM38510-65352BDA, JM38510-65352BCA, SN74HCT74ADBR, SN74HCT74D Datasheet
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SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS169B ± DECEMBER 1982 ± REVISED MAY 1997
DInputs Are TTL-Voltage Compatible
DPackage Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
The 'HCT74 contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the
SN54HCT74 . . . J OR W PACKAGE SN74HCT74 . . . D, N, OR PW PACKAGE
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VCC |
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1CLR |
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1 |
14 |
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1D |
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2 |
13 |
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2CLR |
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1CLK |
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3 |
12 |
2D |
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2CLK |
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1PRE |
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4 |
11 |
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1Q |
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5 |
10 |
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2PRE |
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2Q |
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1Q |
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6 |
9 |
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GND |
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7 |
8 |
2Q |
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SN54HCT74 . . . FK PACKAGE
(TOP VIEW)
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54HCT74 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74HCT74 is characterized for operation from ±40°C to 85°C.
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1D |
1CLR |
NC |
V |
2CLR |
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CC |
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1CLK |
3 |
2 |
1 |
20 19 |
2D |
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4 |
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18 |
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NC |
5 |
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17 |
NC |
1PRE |
6 |
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16 |
2CLK |
NC |
7 |
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15 |
NC |
1Q |
8 |
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14 |
2PRE |
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9 10 11 12 13 |
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1Q |
GND |
NC |
2Q |
2Q |
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NC ± No internal connection |
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FUNCTION TABLE
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INPUTS |
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OUTPUT |
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CLK |
D |
Q |
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PRE |
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CLR |
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Q |
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L |
H |
X |
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H |
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L |
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H |
L |
X |
X |
L |
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H |
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L |
L |
X |
X |
H² |
H² |
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H |
H |
° |
H |
H |
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L |
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H |
H |
° |
L |
L |
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H |
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H |
H |
L |
X |
Q0 |
Q0 |
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²This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS169B ± DECEMBER 1982 ± REVISED MAY 1997
logic symbol²
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4 |
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1PRE |
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S |
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3 |
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1Q |
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1CLK |
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C1 |
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2 |
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1D |
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1D |
6 |
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1 |
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1Q |
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1CLR |
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R |
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10 |
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2PRE |
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9 |
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11 |
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2Q |
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2CLK |
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12 |
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2D |
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8 |
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13 |
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2Q |
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2CLR |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic) |
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PRE |
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CLK |
C |
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C |
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Q |
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C |
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TG |
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C |
C |
C |
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C |
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D |
TG |
TG |
TG |
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Q |
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C |
C |
C |
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CLR |
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absolute maximum ratings over operating free-air temperature range³
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. ±0.5 V to 7 V |
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±20 mA |
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±20 mA |
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±25 mA |
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±50 mA |
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 127°C/W |
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 78°C/W |
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 170°C/W |
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±65°C to 150°C |
³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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