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SN54F138, SN74F138 |
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3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS |
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SDFS051B ± MARCH 1987 ± REVISED JULY 1996 |
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D Designed Specifically for High-Speed |
SN54F138 . . . J PACKAGE |
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Memory Decoders and Data Transmission |
SN74F138 . . . D OR N PACKAGE |
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Systems |
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(TOP VIEW) |
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D Incorporates Three Enable Inputs to |
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1 |
16 |
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VCC |
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Simplify Cascading and/or Data Reception |
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B |
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2 |
15 |
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Y0 |
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D Package Options Include Plastic |
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C |
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3 |
14 |
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Y1 |
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Small-Outline Packages, Ceramic Chip |
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G2A |
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4 |
13 |
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Carriers, and Standard Plastic and Ceramic |
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Y3 |
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G2B |
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5 |
12 |
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300-mil DIPs |
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G1 |
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6 |
11 |
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Y4 |
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description |
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Y7 |
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7 |
10 |
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Y5 |
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GND |
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8 |
9 |
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Y6 |
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The |
′F138 |
is |
designed to be used in |
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high-performance |
memory-decoding or data- |
SN54F138 . . . FK PACKAGE |
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routing applications requiring very short |
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propagation |
delay times. In high-performance |
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NC |
CC |
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memory systems, these decoders can be used to |
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A |
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V Y0 |
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minimize the effects of system decoding. When |
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2 |
1 |
20 19 |
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employed with high-speed memories utilizing a |
C |
Y1 |
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4 |
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18 |
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fast enable circuit, the delay times of this decoder |
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G2A |
5 |
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17 |
Y2 |
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and the enable time of the memory are usually |
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NC |
6 |
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16 |
NC |
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less than the typical access time of the memory. |
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G2B |
7 |
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15 |
Y3 |
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This |
means |
that |
the effective system delay |
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G1 |
8 |
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14 |
Y4 |
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introduced by the decoder is negligible. |
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9 |
10 11 12 13 |
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The conditions at the binary-select inputs and the |
Y7 GND NC Y6 Y5 |
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three enable inputs select one of eight output |
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lines. Two active-low and one active-high enable |
NC ± No internal connection |
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inputs reduce the need for external gates or |
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inverters when expanding. A 24-line decoder can |
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be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The SN54F138 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN54F138, SN74F138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDFS051B ± MARCH 1987 ± REVISED JULY 1996
FUNCTION TABLE
ENABLE INPUTS |
SELECT INPUTS |
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OUTPUTS |
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G1 |
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C |
B |
A |
Y0 |
Y1 |
Y2 |
Y3 |
Y4 |
Y5 |
Y6 |
Y7 |
G2A |
G2B |
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X |
H |
X |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
H |
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X |
X |
H |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
H |
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L |
X |
X |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
H |
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H |
L |
L |
L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
H |
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H |
L |
L |
L |
L |
H |
H |
L |
H |
H |
H |
H |
H |
H |
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H |
L |
L |
L |
H |
L |
H |
H |
L |
H |
H |
H |
H |
H |
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H |
L |
L |
L |
H |
H |
H |
H |
H |
L |
H |
H |
H |
H |
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H |
L |
L |
H |
L |
L |
H |
H |
H |
H |
L |
H |
H |
H |
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H |
L |
L |
H |
L |
H |
H |
H |
H |
H |
H |
L |
H |
H |
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H |
L |
L |
H |
H |
L |
H |
H |
H |
H |
H |
H |
L |
H |
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H |
L |
L |
H |
H |
H |
H |
H |
H |
H |
H |
H |
H |
L |
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logic symbols (alternatives)²
1 |
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BIN/OCT |
0 |
15 |
Y0 |
1 |
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DMUX |
0 |
15 |
Y0 |
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A |
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1 |
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A |
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0 |
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2 |
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14 |
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2 |
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0 |
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14 |
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B |
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2 |
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1 |
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Y1 |
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B |
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G |
7 |
1 |
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Y1 |
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13 |
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13 |
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3 |
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3 |
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C |
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4 |
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2 |
12 |
Y2 |
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C |
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2 |
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2 |
12 |
Y2 |
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3 |
Y3 |
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3 |
Y3 |
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6 |
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& |
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11 |
6 |
& |
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11 |
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G1 |
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4 |
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Y4 |
G1 |
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4 |
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Y4 |
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4 |
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EN |
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10 |
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4 |
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10 |
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G2A |
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5 |
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Y5 |
G2A |
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5 |
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Y5 |
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5 |
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6 |
9 |
Y6 |
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5 |
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6 |
9 |
Y6 |
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G2B |
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7 |
G2B |
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7 |
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7 |
Y7 |
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7 |
Y7 |
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² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |