Texas Instruments JM38510-33701BFA, JM38510-33701B2A, JM38510-33701BEA, SN54F138J, SN74F138D Datasheet

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SN54F138, SN74F138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

 

 

SDFS051B ± MARCH 1987 ± REVISED JULY 1996

 

 

 

 

 

 

 

 

 

 

D Designed Specifically for High-Speed

SN54F138 . . . J PACKAGE

Memory Decoders and Data Transmission

SN74F138 . . . D OR N PACKAGE

Systems

 

 

 

(TOP VIEW)

 

 

 

 

 

 

 

 

 

 

 

 

 

D Incorporates Three Enable Inputs to

 

 

A

 

 

1

16

 

VCC

 

 

 

 

 

Simplify Cascading and/or Data Reception

 

 

 

 

 

 

B

 

 

2

15

 

Y0

D Package Options Include Plastic

 

 

 

 

 

 

C

 

3

14

 

Y1

Small-Outline Packages, Ceramic Chip

 

G2A

 

 

4

13

 

Y2

Carriers, and Standard Plastic and Ceramic

 

 

 

 

 

 

 

 

Y3

 

G2B

 

 

5

12

 

300-mil DIPs

 

G1

 

 

6

11

 

Y4

description

 

Y7

 

7

10

 

Y5

GND

 

 

8

9

 

Y6

 

 

 

The

′F138

is

designed to be used in

 

 

 

 

 

 

high-performance

memory-decoding or data-

SN54F138 . . . FK PACKAGE

routing applications requiring very short

 

 

(TOP VIEW)

 

propagation

delay times. In high-performance

 

 

 

NC

CC

 

memory systems, these decoders can be used to

 

B

A

 

 

V Y0

 

minimize the effects of system decoding. When

 

3

2

1

20 19

 

employed with high-speed memories utilizing a

C

Y1

4

 

 

18

fast enable circuit, the delay times of this decoder

 

 

G2A

5

 

 

17

Y2

and the enable time of the memory are usually

 

 

NC

6

 

 

16

NC

less than the typical access time of the memory.

 

 

G2B

7

 

 

15

Y3

This

means

that

the effective system delay

 

 

G1

8

 

 

14

Y4

introduced by the decoder is negligible.

 

 

 

9

10 11 12 13

 

The conditions at the binary-select inputs and the

Y7 GND NC Y6 Y5

three enable inputs select one of eight output

lines. Two active-low and one active-high enable

NC ± No internal connection

inputs reduce the need for external gates or

 

inverters when expanding. A 24-line decoder can

 

be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN54F138 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

1

Texas Instruments JM38510-33701BFA, JM38510-33701B2A, JM38510-33701BEA, SN54F138J, SN74F138D Datasheet

SN54F138, SN74F138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SDFS051B ± MARCH 1987 ± REVISED JULY 1996

FUNCTION TABLE

ENABLE INPUTS

SELECT INPUTS

 

 

 

OUTPUTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1

 

 

 

 

C

B

A

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

G2A

G2B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

H

X

X

X

X

H

H

H

H

H

H

H

H

X

X

H

X

X

X

H

H

H

H

H

H

H

H

L

X

X

X

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

L

H

H

H

H

H

L

H

H

H

H

H

L

L

H

L

L

H

H

H

H

L

H

H

H

H

L

L

H

L

H

H

H

H

H

H

L

H

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

logic symbols (alternatives)²

1

 

BIN/OCT

0

15

Y0

1

 

DMUX

0

15

Y0

 

 

A

 

 

1

 

 

 

 

A

 

 

0

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

14

 

2

 

 

0

 

14

 

 

 

B

 

 

2

 

 

1

 

Y1

 

B

 

 

 

G

7

1

 

Y1

 

 

 

 

13

 

 

13

3

 

 

 

 

 

3

 

 

 

 

 

 

 

C

 

 

4

 

 

2

12

Y2

 

C

 

 

2

 

 

2

12

Y2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

Y3

 

 

 

 

 

 

 

3

Y3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

&

 

11

6

&

 

 

11

 

 

 

 

 

 

 

 

 

G1

 

 

 

 

4

 

Y4

G1

 

 

 

 

4

 

Y4

 

 

 

 

 

 

 

 

 

 

 

4

 

 

EN

 

10

 

 

 

4

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

G2A

 

 

5

 

Y5

G2A

 

 

 

5

 

Y5

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

6

9

Y6

 

5

 

 

 

6

9

Y6

G2B

 

 

 

7

G2B

 

 

 

7

 

 

 

 

 

 

 

 

7

Y7

 

 

 

 

 

 

 

7

Y7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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