Texas Instruments JM38510-65308BEA, JM38510-65308BFA, SN54HC175J, SN74HC175APWR, SN74HC175D Datasheet

SN54HC175, SN74HC175

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

	SCLS299A ± JANUARY 1996 ± REVISED MAY 1997
D Contain Four Flip-Flops With Double-Rail	SN54HC175 . . . J OR W PACKAGE
Outputs	SN74HC175 . . . D, N, OR PW PACKAGE
D Applications Include:						(TOP VIEW)
± Buffer/Storage Registers
	CLR					1	16		VCC
± Shift Registers
		1Q				2	15		4Q
± Pattern Generators
		1Q				3	14		4Q
D Package Options Include Plastic
		1D				4	13		4D
Small-Outline (D), Thin Shrink		2D				5	12		3D
Small-Outline (PW), and Ceramic Flat (W)
		2Q				6	11		3Q
Packages, Ceramic Chip Carriers (FK), and		2Q				7	10		3Q
Standard Plastic (N) and Ceramic (J)	GND					8	9		CLK
300-mil DIPs
description	SN54HC175 . . . FK PACKAGE
						(TOP VIEW)

These monolithic positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The 'HC175 feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

	1Q	CLR	NC	V	4Q
				CC
1Q	3	2	1	20 19		4Q
	4				18
1D	5				17	4D
NC	6				16	NC
2D	7				15	3D
2Q	8				14	3Q
	9	10 11 12 13
	2Q	GND	NC	CLK	3Q

NC ± No internal connection

The SN54HC175 is characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74HC175 is characterized for operation from ±40°C to 85°C.

FUNCTION TABLE (each flip-flop)

		INPUTS		OUTPUTS
		CLK	D	Q
	CLR					Q
	L	X	X	L		H
	H	↑	H	H		L
	H	↑	L	L		H
	H	L	X	Q0
					Q		0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

SN54HC175, SN74HC175

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS299A ± JANUARY 1996 ± REVISED MAY 1997

logic symbol²

	1		R
CLR
9				C1
CLK
4						2	1Q
						3
1D			1D
							1Q
						7
5							2Q
						6
2D
							2Q
						10
12							3Q
						11
3D
							3Q
						15
13							4Q
						14
4D
							4Q

² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages.

logic diagram (positive logic)

CLR	1
CLK	9
1D	4	2
	1D
		1Q
	C1	3
	R
		1Q

To Three Other Channels

Pin numbers shown are for the D, J, N, PW, and W packages.

absolute maximum ratings over operating free-air temperature range³

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 149°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265