Texas Instruments JM38510-32501BSA, JM38510-32501BRA, JM38510-32501B2A, SN54LS273J, SN74LS273J Datasheet
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SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SDLS090 ± OCTOBER 1976 ± REVISED MARCH 1988
•Contains Eight Flip-Flops With Single-Rail Outputs
•Buffered Clock and Direct Clear Inputs
•Individual Data Input to Each Flip-Flop
•Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
description
These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.
SN54273, SN74LS273 . . . J OR W PACKAGE
SN74273 . . . N PACKAGE
SN74LS273 . . . DW OR N PACKAGE
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(TOP VIEW) |
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VCC |
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CLR |
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1 |
20 |
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1Q |
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2 |
19 |
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8Q |
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1D |
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3 |
18 |
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8D |
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2D |
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4 |
17 |
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7D |
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2Q |
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5 |
16 |
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7Q |
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3Q |
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6 |
15 |
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6Q |
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3D |
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7 |
14 |
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6D |
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4D |
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8 |
13 |
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5D |
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4Q |
9 |
12 |
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5Q |
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GND |
10 |
11 |
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CLK |
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Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output.
These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ′273 and 10 milliwatts for the ′LS273.
SN54LS273 . . . FK PACKAGE
(TOP VIEW)
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1D |
1Q |
CLR |
CC |
8Q |
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V |
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2D |
3 |
2 |
1 |
20 19 |
8D |
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4 |
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18 |
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2Q |
5 |
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17 |
7D |
3Q |
6 |
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16 |
7Q |
3D |
7 |
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15 |
6Q |
4D |
8 |
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14 |
6D |
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9 |
10 11 12 13 |
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4Q |
GND |
CLK |
5Q |
5D |
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FUNCTION TABLE |
logic symbol² |
(each flip-flop) |
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INPUTS |
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OUTPUT |
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1 |
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Q |
CLR |
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CLEAR |
CLOCK |
D |
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11 |
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L |
X |
X |
L |
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CLK |
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H |
↑ |
H |
H |
3 |
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1D |
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H |
↑ |
L |
L |
4 |
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2D |
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H |
L |
X |
Q0 |
7 |
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3D |
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8 |
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4D |
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13
5D
14
6D
17
7D
18
8D
EN |
C1 |
2
1D |
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1Q |
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5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
² This symbol is in accordance with ANSI/IEEE Std.
91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, J, N, and W packages.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1988, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SDLS090 ± OCTOBER 1976 ± REVISED MARCH 1988
schematics of inputs and outputs
′273
EQUIVALENT OF EACH INPUT
VCC
Req
INPUT
Clear: Req = 3 kW NOM
Clock: Req = 6 kW NOM
All other inputs: Req = 8 kW NOM
′LS273
TYPICAL OF ALL OUTPUTS
VCC
100 W
NOM
OUTPUT
EQUIVALENT OF EACH INPUT |
TYPICAL OF ALL OUTPUTS |
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VCC |
VCC |
120 W NOM |
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20 kW
NOM
INPUT
OUTPUT
logic diagram (positive logic)
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1D |
2D |
3D |
4D |
5D |
6D |
7D |
8D |
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CLOCK |
11 |
3 |
4 |
7 |
8 |
13 |
14 |
17 |
18 |
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1D |
1D |
1D |
1D |
1D |
1D |
1D |
1D |
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C1 |
C1 |
C1 |
C1 |
C1 |
C1 |
C1 |
C1 |
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R |
R |
R |
R |
R |
R |
R |
R |
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CLEAR |
1 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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1Q |
2Q |
3Q |
4Q |
5Q |
6Q |
7Q |
8Q |
Pin numbers shown are for the DW, J, N, and W packages.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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