Texas Instruments JM38510-34101B2A, JM38510-34101BDA, JM38510-34101BCA, SN54F74J, SN74F74D Datasheet
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SN54F74, SN74F74 |
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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
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WITH CLEAR AND PRESET |
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SDFS046A ± MARCH 1987 ± REVISED OCTOBER 1993 |
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• Package Options Include Plastic |
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SN54F74 . . . J PACKAGE |
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Small-Outline Packages, Ceramic Chip |
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SN74F74 . . . D OR N PACKAGE |
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Carriers, and Standard Plastic and Ceramic |
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(TOP VIEW) |
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300-mil DIPs |
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1CLR |
1 |
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14 |
VCC |
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description |
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1D |
2 |
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13 |
2CLR |
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These devices contain two independent positive- |
1CLK |
3 |
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12 |
2D |
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1PRE |
4 |
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11 |
2CLK |
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edge-triggered D-type flip-flops. A low level at the |
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1Q |
5 |
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10 |
2PRE |
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preset (PRE) or clear (CLR) inputs sets or resets |
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1Q |
6 |
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9 |
2Q |
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the outputs regardless of the levels of the other |
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GND |
7 |
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8 |
2Q |
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inputs. When PRE and CLR are inactive (high), |
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data at the data (D) input meeting the setup time |
SN54F74 . . . FK PACKAGE |
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requirements is transferred to the outputs on the |
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(TOP VIEW) |
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positive-going edge of the clock pulse. Clock |
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1D |
1CLR |
NC |
V |
2CLR |
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directly related to the rise time of the clock pulse. |
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triggering occurs at a voltage level and is not |
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CC |
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Following the hold-time |
interval, data at |
the |
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3 |
2 |
1 |
20 19 |
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D input may be changed without affecting the |
1CLK |
2D |
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levels at the outputs. |
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4 |
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18 |
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NC |
5 |
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17 |
NC |
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The SN54F74 is characterized for operation over |
1PRE |
6 |
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16 |
2CLK |
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° |
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NC |
7 |
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15 |
NC |
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the full military temperature range of ±55 C to |
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The |
SN74F74 |
is |
characterized |
for |
1Q |
8 |
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14 |
2PRE |
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125 C. |
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9 |
10 11 12 13 |
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operation from 0°C to 70°C. |
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GND |
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FUNCTION TABLE |
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1Q |
NC |
2Q |
2Q |
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INPUTS |
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OUTPUTS |
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NC ± No internal connection |
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CLK |
D |
Q |
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PRE |
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CLR |
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Q |
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L |
H |
X |
X |
H |
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L |
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H |
L |
X |
X |
L |
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H |
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L |
L |
X |
X |
H² |
H² |
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H |
H |
↑ |
H |
H |
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L |
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H |
H |
↑ |
L |
L |
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H |
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H |
H |
L |
X |
Q0 |
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Q |
0 |
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²The output levels are not guaranteed to meet the
minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when PRE or CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2±1 |
SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A ± MARCH 1987 ± REVISED OCTOBER 1993
logic symbol²
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4 |
S |
5 |
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1PRE |
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1Q |
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3 |
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C1 |
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1CLK |
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2 |
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1D |
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1D |
6 |
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1 |
R |
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1Q |
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1CLR |
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10 |
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9 |
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2PRE |
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2Q |
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11 |
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2CLK |
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12 |
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2D |
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8 |
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13 |
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2Q |
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2CLR |
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² This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
logic diagram, each flip-flop (positive logic)
PRE
CLK |
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C |
C |
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C |
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Q |
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TG |
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C |
C |
C |
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C |
D |
TG |
TG |
TG |
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Q |
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C |
C |
C |
CLR |
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)³
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . ±0.5 V to 7 V |
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. ±1.2 V to 7 V |
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±30 mA to 5 mA |
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.5 V to VCC |
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 40 mA |
Operating free-air temperature range: SN54F74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±55°C to 125°C |
SN74F74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 0°C to 70°C |
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±65°C to 150°C |
³Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
2±2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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