Samsung K4H561638B-TLB0, K4H561638B-TLA2, K4H561638B-TLA0, K4H561638B-TCB0, K4H560838B-TLA2 Datasheet

256Mb DDR SDRAM		Preliminary

DDR SDRAM Specification

Version 0.3

- 1 -

REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

Revision History

Version 0 (May, 2000)

- First version for internal review of 256Mb B-die.

Version 0.1(July,2000)

-Added DC target spec values

-Deleted tDAL in AC parameter X

Version 0.2(October,2000) - Updated DC current spec

Version 0.3(November,2000)

- Changed spec to preliminery from target

- 2 -

REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

Contents

Revision History

General Information

1.Key Features

1.1Features

1.2Operating Frequencies

2.Package Pinout & Dimension

2.1Package Pintout

2.2Input/Output Function Description

2.366 Pin TSOP(II)/MS-024FC Package Physical Dimension

3.Functional Description

3.1Simplified State Diagram

3.2Basic Functionality

3.2.1Power-Up Sequence

3.2.2Mode Register Definition

3.2.2.1Mode Register Set(MRS)

3.2.2.2Extended Mode Register Set(EMRS)

3.2.3Precharge

3.2.4No Operation(NOP) & Device Deselect

3.2.5Row Active

3.2.6Read Bank

3.2.7Write Bank

3.3Essential Functionality for DDR SDRAM

3.3.1Burst Read Operation

3.3.2Burst Write Operation

3.3.3Read Interrupted by a Read

3.3.4Read Interrupted by a Write & Burst Stop

3.3.5Read Interrupted by a Precharge

3.3.6Write Interrupted by a Write

2

7

8

8

8

9

9

10

11

12

12

13

13

14

14

16

17

17

18

18

18

19

19

20

21

21

22

23

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

3.3.7Write Interrupted by a Read & DM

3.3.8Write Interrupted by a Precharge & DM

3.3.9Burst Stop

3.3.10DM masking

3.3.11Read With Auto Precharge

3.3.12Write With Auto Precharge

3.3.13Auto Refresh & Self Refresh

3.3.14Power Down

4.Command Truth Table

5.Functional Truth Table

6.Absolute Maximum Rating

7.DC Operating Conditions & Specifications

7.1DC Operating Conditions

7.2DDR SSDRAM spec Items and Test Conditions

7.3DDR SDRAM IDD spec Table

8.AC Operating Conditions & Timming Specification

8.1AC Operating Conditions

8.2AC Timming Parameters & Specification

9.AC Operating Test Conditions

10.Input/Output Capacitance

11.IBIS: I/V Characteristics for Input and Output Buffers

11.1Normal strength driver

11.2Half strength driver

12.QFC function

QFC definition

QFC timming on Read Operation

QFC timming on Write operation with tDQSSmax

QFC timming on Write operation with tDQSSmin

QFC timming example for interrupted writes operation

Timing Diagram

24

25

26

27

28

29

30

31

32

33

37

37

37

38

41

41

42

44

44

45

45

47

49

49

49

50

50

51

52

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary
	List of tables
	Table 1 : Operating frequency and DLL jitter	8
	Table 2. : Column address configurtion	9
	Table 3 : Input/Output function description	10
	Table 4 : Burst address ordering for burst length	15
	Table 5 : Bank selection for precharge by bank address bits	17
	Table 6 : Operating description when new command asserted while	28
	read with auto precharge is issued
	Table 7 : Operating description when new command asserted while	29
	write with auto precharge is issued
	Table 8 : Command truth table	32
	Table 9-1 : Functional truth table	33
	Table 9-2 : Functional truth table (contiued)	34
	Table 9-3 : Functional truth table (contiued)	35
	Table 9-4 : Functional truth table (contiued)	36
	Table 10 : Absolute maximum raings	37
	Table 11 : DC operating condtion	37
	Table 12 : DDR SDRAM spec Items and Test Conditions	38
	Table 13 : DDR SDRAM IDD spec Table	40
	Table 14 : AC operating condition	41
	Table 15 : AC timing parameters and specifications	43
	Table 16 : AC operating test conditions	44
	Table 17 : Input/Output capacitance	44
	Table 18 : Pull down and pull up current values for normal strength driver	46
	Table 19 : Pull down and pull up current values for half strength driver	48

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM				Preliminary
	List of figures
	Figure 1 : 256Mb Package Pinout			6
	Figure 2 : Package dimension			11
	Figure 3 :State digram			12
	Figure 4 : Power up and initialization sequence			13
	Figure 5 : Mode register set			14
	Figure 6 : Mode register set sequence			15
	Figure 7 : Extend mode register set			16
	Figure 8 : Bank activation command cycle timing			18
	Figure 9 : Burst read operation timing			19
	Figure 10 : Burst write operation timing			20
	Figure 11 : Read interrupted by a read timing			21
	Figure 12 : Read interrupted by a write and burst stop timing			21
	Figure 13 : Read interrupted by a precharge timing			22
	Figure 14 : Write interrupted by a write timing			23
	Figure 15 : Write interrupted by a read and DM timing			24
	Figure 16 : Write interrupted by a precharge and DM timing			25
	Figure 17 : Burst stop timing			26
	Figure 18 : DM masking timing			27
	Figure 19 : Read with auto precharge timing			28
	Figure 20 : Write with auto precharge timing			29
	Figure 21 : Auto refresh timing			30
	Figure 22 : Self refresh timing			30
	Figure 23 : Power down entry and exit timing			31
	Figure 24 : Output Load Circuit (SSTL_2)			44
	Figure 25 : I / V characteristics for input/output buffers:			45
		pull-up(above) and pull-down(below) for normal strength driver
	Figure 26 : I / V characteristics for input/output buffers:			47
		pull-up(above) and pull-down(below) for half strength driver
	Figure 27 : QFC timing on read operation			49
	Figure 28 : QFC timing on write operation with tDQSSmax			50
	Figure 29 : QFC timing on write operation with tDQSSmin			50
	Figure 30 : QFC timing example for interrupted writes operation			51

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM

Preliminary

General Information

Organization

133Mhz w/ CL=2

133Mhz w/ CL=2.5

100Mhz w/ CL=2

64Mx4

K4H560438B-TCA2

K4H560438B-TCB0

K4H560438B-TCA0

K4H560438B-TLA2

K4H560438B-TLB0

K4H560438B-TLA0

32Mx8

K4H560838B-TCA2

K4H560838B-TCB0

K4H560838B-TCA0

K4H560838B-TLA2

K4H560838B-TLB0

K4H560838B-TLA0

16Mx16

K4H561638B-TCA2

K4H561638B-TCB0

K4H561638B-TCA0

K4H561638B-TLA2

K4H561638B-TLB0

K4H561638B-TLA0

1

2

3

4

5

6

7

8

9

10

11

K 4 H XX XX X X X - X X XX

Memory

Speed

DRAM

Small Classification

Temperature & Power

Package

Density and Refresh

Version

Organization

Bank

Interface (VDD & VDDQ)

1. SAMSUNG Memory : K

8. Version

2. DRAM : 4

M : 1st Generation

3. Small Classification

A

: 2nd Generation

H

: DDR SDRAM

B

: 3rd Generation

4. Density & Refresh

C

: 4th Generation

64 :

64M

4K/64ms

D : 5th Generation

28 :

128M

4K/64ms

E : 6th Generation

56 :

256M

8K/64ms

9. Package

51 :

512M

8K/64ms

T :

TSOP2 (400mil x 875mil)

1G :

1G 16K/32ms

5. Organization

10. Temperature & Power

C : (Commercial, Normal)

04

: x4

L : (Commercial, Low)

08

: x8

16

: x16

32

: x32

11. Speed

	6. Bank	A0	: 10ns@CL2
		A2	: 7.5ns@CL2
	3 : 4 Bank
		B0	: 7.5ns@CL2.5

7.Interface (VDD & VDDQ)

8: SSTL-2(2.5V, 2.5V)

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

1. Key Features

1.1 Features

•Double-data-rate architecture; two data transfers per clock cycle

•Bidirectional data strobe(DQS)

•Four banks operation

•Differential clock inputs(CK and CK)

•DLL aligns DQ and DQS transition with CK transition

•MRS cycle with address key programs -. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

•All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

•Data I/O transactions on both edges of data strobe

•Edge aligned data output, center aligned data input

•LDM,UDM/DM for write masking only

•Auto & Self refresh

•7.8us refresh interval(8K/64ms refresh)

•Maximum burst refresh cycle : 8

•66pin TSOP II package

1.2 Operating Frequencies

	- A2(DDR266A)	- B0(DDR266B)	- A0(DDR200)
Speed @CL2	133MHz	100MHz	100MHz
Speed @CL2.5	-	133MHz	-
DLL jitter	±0.75ns	±0.75ns	±0.8ns

*CL : Cas Latency

Table 1. Operating frequency and DLL jitter

- 8 -

REV. 0.3 November 2. 2000

16Mb x 16

32Mb x 8

64Mb x 4

256Mb DDR SDRAM		Preliminary

2. Package Pinout & Dimension

2.1 Package Pinout

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

NC

VDDQ

LDQS

NC

VDD

QFC/NC LDM WE

CAS

RAS

CS

NC

BA0

BA1

AP/A10

A0

A1

A2

A3

VDD

VDD

VDD

1

66

VSS

VSS

2

65

NC

DQ7

DQ0

NC

3

64

VSSQ

VSSQ

VDDQ

VDDQ

NC

4

63

NC

NC

NC

5

62

DQ3

DQ6

DQ1

DQ0

6

61

VDDQ

VDDQ

VSSQ

VSSQ

7

60

NC

NC

NC

NC

DQ2

8

59

NC

DQ5

NC

9

58

VSSQ

VSSQ

VDDQ

VDDQ

10

57

NC

NC

NC

NC

66 PIN TSOP(II)

11

56

DQ2

DQ4

DQ3

DQ1

(400mil x 875mil)

VSSQ

VSSQ

12

55

VDDQ

VDDQ

(0.65 mm PIN PITCH)

54

NC

NC

NC

NC

13

Bank Address

53

NC

NC

NC

NC

14

BA0-BA1

52

VSSQ

VSSQ

VDDQ

VDDQ

15

NC

51

DQS

DQS

NC

16

Row Address

50

NC

NC

NC

NC

17

VDD

VDD

18

A0-A12

49

VREF

VREF

48

VSS

VSS

QFC/NC QFC/NC

19

Auto Precharge

NC

NC

20

47

DM

DM

A10

WE

WE

21

46

CK

CK

45

CK

CK

CAS

CAS

22

23

44

CKE

CKE

RAS

RAS

43

NC

NC

CS

CS

24

NC

NC

25

MS-024FC

42

A12

A12

41

A11

A11

BA0

BA0

26

40

A9

A9

BA1

BA1

27

AP/A10

AP/A10

28

39

A8

A8

A0

38

A7

A7

A0

29

37

A6

A6

A1

A1

30

36

A5

A5

A2

A2

31

35

A4

A4

A3

A3

32

VDD

34

VSS

VSS

VDD

33

FIgure 1. 256Mb package Pinout

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

NC

VSSQ

UDQS NC

VREF

VSS

UDM

CK

CK

CKE

NC

A12

A11

A9

A8

A7

A6

A5

A4

VSS

Organization	Column Address
64Mx4	A0-A9, A11
32Mx8	A0-A9
16Mx16	A0-A8

DM is internally loaded to match DQ and DQS identically.

Table 2. Column address configuration

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM

Preliminary

2.2 Input/Output Function Description

SYMBOL

TYPE

DESCRIPTION

CK, CK

Input

Clock : CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to

both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Input

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN

(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,

which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled

during power-down and self refresh modes, providing low standby power. CKE will recognize

an LVCMOS LOW level prior to VREF being stable on power-up.

CS

Input

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code.

RAS, CAS, WE

Input

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

LDM,(U)DM

Input

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-

ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on

DQ8-DQ15.

BA0, BA1

Input

Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRE-

CHARGE command is being applied.

A [n : 0]

Input

Address Inputs : Provide the row address for ACTIVE commands, the column address and

AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-

ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-

mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also

provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which

mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).

DQ

I/O

Data Input/Output : Data bus

LDQS,(U)DQS

I/O

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on

DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.

QFC

Output

FET Control : Optional. Output during every Read and Write access. Can be used to control

isolation switches on modules.

NC

-

No Connect : No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply : +2.5V ± 0.2V.

VSSQ

Supply

DQ Ground.

VDD

Supply

Power Supply : +2.5V ± 0.2V (device specific).

VSS

Supply

Ground.

VREF

Input

SSTL_2 reference voltage.

Table 3. Input/Output Function Description

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
												Units : Millimeters
			#66		#34			(0.80)											(0.50)
					0.10														(10.76)		0.20
	(1.50)				10.16±				(10× )										(10× )		11.76±
			#1		#33			(0.80)	0.125						+0.075-0.035				(0.50)
			(1.50)
0.665± 0.05 0.210± 0.05				22.22± 0.10		1.00± 0.10	1.20MAX													0.45~0.75
	(				(10× )							)							)
	R0.																		5
	1										×								.2
		5)							(	4									(R0
		)						0.10 MAX								2	5	)
															.				0.25TYP
	5		(0.71)	0.65TYP	0.30± 0.08									0
	.1					MIN							R
	0			0.65± 0.08			[	0.075 MAX ]				(
	(R				(10× )
						0.05
NOTE																			0× ~8×
1. (	) IS REFERENCE
2. [	] IS ASS’Y OUT QUALITY

Figure 2. Package dimension

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

3.Functional Description

3.1Simplified State Diagram

						SELF
						REFRESH
					REFS
						REFSX
	MODE	MRS				REFA	AUTO
	REGISTER		IDLE
						REFRESH
	SET
						CKEL
	POWER			CKEH
			ACT
	DOWN					POWER
		CKEL				DOWN
		CKEH
			ROW
			ACTIVE			BURST STOP
		WRITE				READ
			WRITEA	READA
	WRITEA		READ			READ
	WRITEA					READA
				READA
			PRE
	WRITEA					READA
			PRE		PRE
POWER	POWER		PRE
APPLIED		PRE
	ON		CHARGE
							Automatic Sequence
							Command Sequence

WRITEA : Write with autoprecharge

READA : Read with autoprecharge

Figure 3. State diagram

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

3.2Basic Functionality

3.2.1Power-Up and Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1.Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)

-Apply VDD before or at the same time as VDDQ.

-Apply VDDQ before or at the same time as VTT & Vref.

2.Start clock and maintain stable condition for a minimum of 200us.

3.The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.

4.Issue precharge commands for all banks of the device.

*1	5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
	to all of the rest address pins, A1~A11 and BA1)
*1	6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
	lock the DLL.
*2	(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
	7. Issue precharge commands for all banks of the device.

8.Issue 2 or more auto-refresh commands.

9.Issue a mode register set command with low to A8 to initialize device operation.

*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6 & 7 is regardless of the order.

Power up & Initialization Sequence
0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
CK
CK
	tRP		2 Clock min.		2 Clock min.		tRP			tRFC				tRFC			2 Clock min.
Command
								1st Auto					2nd Auto				Mode		Any
precharge		EMRS		MRS		precharge
ALL Banks			DLL Reset			ALL Banks		Refresh					Refresh			Register Set		Command
											min.200 Cycle

Figure 4. Power up and initialization sequence

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

3.2.2 Mode Register Definition

3.2.2.1 Mode Register Set(MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst lengths, addressing modes and CAS latencies.

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

RFU				0				RFU						DLL				TM				CAS Latency						BT				Burst Length							Mode Register
								A8		DLL Reset									A7			mode						A3			Burst Type
								0			No							0				Normal						0			Sequential
								1			Yes							1				Test						1			Interleave
																														Burst Length
															CAS Latency
																															A2		A1			A0			Latency
															A6				A5			A4		Latency															Sequential	Interleave
															0			0				0		Reserve						0			0			0			Reserve	Reserve
	BA0						An ~ A0
	0				(Existing)MRS Cycle										0			0				1		Reserve						0			0			1		2		2
															0			1				0		2						0			1			0		4		4
	1			Extended Funtions(EMRS)
															0			1				1		(3)						0			1			1		8		8
															1			0				0		Reserve						1			0			0			Reserve	Reserve
	* RFU(Reserved for future use)														1			0				1		(1.5)						1			0			1			Reserve	Reserve
	should stay "0" during MRS														1			1				0		2.5						1			1			0			Reserve	Reserve
	cycle.
															1			1				1		Reserve						1			1			1			Reserve	Reserve

Figure 5. Mode Register Set

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM						Preliminary
			Burst Address Ordering for Burst Length
		Burst	Starting	Sequential Mode		Interleave Mode
		Length	Address(A2, A1, A0)
		2	xx0	0,	1	0, 1
			xx1	1,	0	1, 0
			x00	0, 1,	2, 3	0, 1, 2, 3
		4	x01	1, 2, 3, 0		1, 0, 3, 2
			x10	2, 3, 0, 1		2, 3, 0, 1
			x11	3, 0, 1, 2		3, 2, 1, 0
			000	0, 1, 2, 3, 4, 5, 6, 7		0, 1, 2, 3, 4, 5, 6, 7
			001	1, 2, 3, 4, 5, 6, 7, 0		1, 0, 3, 2, 5, 4, 7, 6
			010	2, 3, 4, 5, 6, 7, 0, 1		2, 3, 0, 1, 6, 7, 4, 5
		8	011	3, 4, 5, 6, 7, 0, 1, 2		3, 2, 1, 0, 7, 6, 5, 4
			100	4, 5, 6, 7, 0, 1, 2, 3		4, 5, 6, 7, 0, 1, 2, 3
			101	5, 6, 7, 0, 1, 2, 3, 4		5, 4, 7, 6, 1, 0, 3, 2
			110	6, 7, 0, 1, 2, 3, 4, 5		6, 7, 4, 5, 2, 3, 0, 1
			111	7, 0, 1, 2, 3, 4, 5, 6		7, 6, 5, 4, 3, 2, 1, 0

Table 4. Burst address ordering for burst length

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the normal drive strength and weak drive strength will be included in a future revision of this document.

Mode Register Set
0	1	2	3	4	5	6	7	8
CK
CK
			*1
Command	Precharge		Mode		Any
	All Banks		Register Set		Command
	tCK	tRP*2		2 Clock min.

*1 : MRS can be issued only at all bank precharge state. *2 : Minimum tRP is required to issue MRS command.

Figure 6. Mode Register Set sequence

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REV. 0.3 November 2. 2000

256Mb DDR SDRAM		Preliminary

3.2.2.2 Extended Mode Register Set(EMRS)

The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver size. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

BA1

BA0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address Bus

RFU

1

RFU : Must be set "0"

QFC

D.I.C

DLL

Extended Mode Register

Output Driver Impedence Control			A0	DLL Enable
0	Normal		0	Enable
1	Weak		1	Disable

BA0	An ~ A0
0	(Existing)MRS Cycle
1	Extended Funtions(EMRS)

QFC control

0Disable(Default)

1Enable

Figure 7. Extend Mode Register set

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REV. 0.3 November 2. 2000