Samsung K4S560432A-TC-L1L, K4S560432A-TC-L1H, K4S560432A-TC-L80, K4S560432A-TC-L75 Datasheet

K4S560432A

CMOS SDRAM

256Mbit SDRAM

16M x 4bit x 4 Banks Synchronous DRAM LVTTL

Revision 0.0

Sep. 1999

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Sep. 1999

K4S560432A

CMOS SDRAM

16M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

• JEDEC standard 3.3V power supply

The K4S560432A is 268,435,456 bits synchronous high data

•

LVTTL compatible with multiplexed address

rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits,

•

Four banks operation

fabricated with SAMSUNG's high performance CMOS technol-

•

MRS cycle with address key programs

ogy. Synchronous design allows precise cycle control with the use

-. CAS latency (2 & 3)

of system clock I/O transactions are possible on every clock cycle.

-. Burst length (1, 2, 4, 8 & Full page)

Range of operating frequencies, programmable burst length and

-. Burst type (Sequential & Interleave)

programmable latencies allow the same device to be useful for a

• All inputs are sampled at the positive going edge of the system

variety of high bandwidth, high performance memory system

clock.

applications.

•

Burst read single-bit write operation

•

DQM for masking

ORDERING INFORMATION

•

Auto & self refresh

•

64ms refresh period (8K cycle)

Part No.

Max Freq.

Interface

Package

K4S560432A-TC/L75

133MHz(CL=3)

K4S560432A-TC/L80

125MHz(CL=3)

LVTTL

54pin

K4S560432A-TC/L1H

100MHz(CL=2)

TSOP(II)

K4S560432A-TC/L1L

100MHz(CL=3)

FUNCTIONAL BLOCK DIAGRAM

I/O

LWE

Data Input Register

Control

LDQM

Bank Select

	Address		CounterRefresh	BufferRow	DecoderRow			16M x 4	AMPSense	BufferOutput
								16M x 4			DQi
								16M x 4
CLK								16M x 4
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR		LDQM
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Sep. 1999

K4S560432A

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

1

54

VSS

N.C

2

53

N.C

VDDQ

3

52

VSSQ

N.C

4

51

N.C

DQ0

5

50

DQ3

VSSQ

6

49

VDDQ

N.C

7

48

N.C

N.C

8

47

N.C

VDDQ

9

46

VSSQ

N.C

10

45

N.C

DQ1

11

44

DQ2

VSSQ

12

43

VDDQ

N.C

13

42

N.C

VDD

14

41

VSS

N.C

15

40

N.C/RFU

WE

16

39

DQM

CAS

17

38

CLK

RAS

18

37

CKE

CS

19

36

A12

BA0

20

35

A11

BA1

21

34

A9

A10/AP

22

33

A8

A0

23

32

A7

A1

24

31

A6

54Pin TSOP (II)

A2

25

30

A5

(400mil x 875mil)

A3

26

29

A4

(0.8 mm Pin pitch)

VDD

27

28

VSS

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CS

Chip select

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE

Clock enable

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A12

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

RAS

Row address strobe

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

CAS

Column address strobe

Enables column access.

Enables write operation and row precharge.

WE

Write enable

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ 3

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

This pin is recommended to be left No Connection on the device.

/reserved for future use

Rev. 0.0 Sep. 1999