Samsung K4S280832M-TC-L10, K4S280832M-TC-L1L, K4S280832M-TC-L1H Datasheet

K4S280832M

CMOS SDRAM

128Mbit SDRAM

4M x 8Bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.0

Aug. 1999

Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Aug. 1999

K4S280832M

CMOS SDRAM

4M x 8Bit x 4 Banks Synchronous DRAM

FEATURES

•JEDEC standard 3.3V power supply

•LVTTL compatible with multiplexed address

•Four banks operation

•MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

•All inputs are sampled at the positive going edge of the system clock.

•Burst read single-bit write operation

•DQM for masking

•Auto & self refresh

•64ms refresh period (4K cycle)

GENERAL DESCRIPTION

The K4S280832M is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

Part No.	Max Freq.	Inter-	Package
K4S280832M-TC/L80	125MHz(CL=3)
K4S280832M-TC/L1H	100MHz(CL=2)	LVTTL	54pin
K4S280832M-TC/L1L	100MHz(CL=3)		TSOP(II)
K4S280832M-TC/L10	66MHz(CL=2 &3)

FUNCTIONAL BLOCK DIAGRAM

							Data Input Register
		Bank Select
	Address		CounterRefresh	BufferRow	DecoderRow			4M x 8	AMPSense
								4M x 8
								4M x 8
CLK								4M x 8
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM

	I/O					LWE
	Control					LDQM
	Output					DQi
	Buffer

LDQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Aug. 1999

K4S280832M

CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

1

54

VSS

DQ0

2

53

DQ7

VDDQ

3

52

VSSQ

N.C

4

51

N.C

DQ1

5

50

DQ6

VSSQ

6

49

VDDQ

N.C

7

48

N.C

DQ2

8

47

DQ5

VDDQ

9

46

VSSQ

N.C

10

45

N.C

DQ3

11

44

DQ4

VSSQ

12

43

VDDQ

N.C

13

42

N.C

VDD

14

41

VSS

N.C

15

40

N.C/RFU

WE

16

39

DQM

CAS

17

38

CLK

RAS

18

37

CKE

CS

19

36

N.C

BA0

20

35

A11

BA1

21

34

A9

A10/AP

22

33

A8

A0

23

32

A7

A1

24

31

A6

A2

25

30

A5

54Pin TSOP (II)

A3

26

29

A4

(400mil x 875mil)

VDD

27

28

VSS

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CS

Chip select

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE

Clock enable

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

RAS

Row address strobe

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

CAS

Column address strobe

Enables column access.

Enables write operation and row precharge.

WE

Write enable

Latches data in starting from CAS, WE active.

DQM

Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ 7

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

This pin is recommended to be left No Connection on the device.

/reserved for future use

Rev. 0.0 Aug. 1999