Samsung K4S161622D-TC-L80, K4S161622D-TC-L70, K4S161622D-TC-L60, K4S161622D-TC-L55, K4S161622D-TC-L10 Datasheet

K4S161622D

CMOS SDRAM

512K x 16Bit x 2 Banks Synchronous DRAM

FEATURES

•3.3V power supply

•LVTTL compatible with multiplexed address

•Dual banks operation

•MRS cycle with address key programs

-. CAS Latency ( 2 & 3)

-. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave)

•All inputs are sampled at the positive going edge of the system clock

•Burst Read Single-bit Write operation

•DQM for masking

•Auto & self refresh

•15.6us refresh duty cycle (2K/32ms)

GENERAL DESCRIPTION

The K4S161622D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

	Part NO.	MAX Freq.	Interface	Package
	K4S161622D-TC/L55	183MHz
	K4S161622D-TC/L60	166MHz		50
	K4S161622D-TC/L70	143MHz	LVTTL
				TSOP(II)
	K4S161622D-TC/L80	125MHz
	K4S161622D-TC/L10	100MHz

FUNCTIONAL BLOCK DIAGRAM

							Data Input Register
		Bank Select			DecoderRow
	Address		CounterRefresh	BufferRow			512K x 16
CLK	Register		LRAS	LCBR	Buffer.Col		512K x 16
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	L(U)DQM

AMP Sense

	I/O					LWE
	Control					LDQM
	Output					DQi
	Buffer

LDQM

*Samsung Electronics reserves the right to change products or specification without notice.

K4S161622D

CMOS SDRAM

PIN CONFIGURATION (TOP VIEW)

VDD

1

50

VSS

DQ0

2

49

DQ15

DQ1

3

48

DQ14

VSSQ

4

47

VSSQ

DQ2

5

46

DQ13

DQ3

6

45

DQ12

VDDQ

7

44

VDDQ

DQ4

8

43

DQ11

DQ5

9

42

DQ10

VSSQ

10

41

VSSQ

DQ6

11

40

DQ9

DQ7

12

39

DQ8

VDDQ

13

38

VDDQ

LDQM

14

37

N.C/RFU

WE

15

36

UDQM

CAS

16

35

CLK

RAS

17

34

CKE

CS

18

33

N.C

BA

19

32

A9

A10/AP

20

31

A8

A0

21

30

A7

A1

22

29

A6

A2

23

28

A5

50PIN TSOP (II)

A3

24

27

A4

(400mil x 825mil)

VDD

25

26

VSS

(0.8 mm PIN PITCH)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CS

Chip Select

CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE

Clock Enable

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A10/AP

Address

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, column address : CA0 ~ CA7

BA

Bank Select Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

RAS

Row Address Strobe

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

CAS

Column Address Strobe

Enables column access.

Enables write operation and row precharge.

WE

Write Enable

Latches data in starting from CAS, WE active.

L(U)DQM

Data Input/Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ 15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power Supply/Ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data Output Power/Ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No Connection/

This pin is recommended to be left No Connection on the device.

Reserved for Future Use

K4S161622D				CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol	Value		Unit
Voltage on any pin relative to Vss		VIN, VOUT	-1.0 ~ 4.6		V
Voltage on VDD supply relative to Vss		VDD, VDDQ	-1.0 ~ 4.6		V
Storage temperature		TSTG	-55 ~ +150		°C
Power dissipation		PD	1		W
Short circuit current		IOS	50		mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit	Note
Supply voltage	VDD, VDDQ	3.0	3.3	3.6	V	4
Input logic high votlage	VIH	2.0	3.0	VDDQ+0.3	V	1
Input logic low voltage	VIL	-0.3	0	0.8	V	2
Output logic high voltage	VOH	2.4	-	-	V	IOH = -2mA
Output logic low voltage	VOL	-	-	0.4	V	IOL = 2mA
Input leakage current	ILI	-10	-	10	uA	3

Note: : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2.VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3.Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4.The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin

Symbol

Min

Max

Unit

Clock

CCLK

2

4

pF

RAS, CAS, WE, CS, CKE, L(U)DQM

CIN

2

4

pF

Address

CADD

2

4

pF

DQ0 ~ DQ15

COUT

3

5

pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter	Symbol	Value	Unit
Decoupling Capacitance between VDD and VSS	CDC1	0.1 + 0.01	uF
Decoupling Capacitance between VDDQ and VSSQ	CDC2	0.1 + 0.01	uF

Note : 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2.VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

K4S161622D									CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter	Symbol	Test Condition				CAS		Version					Unit	Note
						Latency	-55	-60	-70	-80		-10
Operating Current			Burst Length =1			3	120	115	105		95	85
	ICC1		tRC³tRC(min)										mA	2
(One Bank Active)						2	-	-	110		95	80
			Io = 0 mA
Precharge Standby Cur-	ICC2P	CKE£VIL(max), tCC = 15ns							2				mA
rent in power-down mode	ICC2PS	CKE & CLK£VIL(max), tCC = ¥							2
		CKE³VIH(min),		³VIH(min), tCC = 15ns
	ICC2N		CS						15
Precharge Standby Current		Input signals are changed one time during 30ns
													mA
in non power-down mode	ICC2NS	CKE³VIH(min), CLK£VIL(max), tCC = ¥							5
		Input signals are stable
Active Standby Current	ICC3P	CKE£VIL(max), tCC = 15ns							3				mA
in power-down mode	ICC3PS	CKE & CLK£VIL(max), tCC = ¥							3
		CKE³VIH(min),		³VIH(min), tCC = 15ns
Active Standby Current	ICC3N		CS						25				mA
		Input signals are changed one time during 30ns
in non power-down mode
		CKE³VIH(min), CLK£VIL(max), tCC = ¥
(One Bank Active)	ICC3NS								15				mA
		Input signals are stable
Operating Current		Io = 0 mA				3	155	150	140		130	115
	ICC4	Page Burst 2Banks Activated											mA	2
(Burst Mode)
		tCCD = 2CLKs				2	-	-	125		115	100
Refresh Current	ICC5	tRC³tRC(min)				3	105	100	90		90	80	mA	3
						2	-	-	100		90	80
Self Refresh Current	ICC6			CKE£0.2V					1				mA	4
									250				uA	5

Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2.Measured with outputs open. Addresses are changed only one time during tcc(min).

3.Refresh period is 32ms. Addresses are changed only one time during tcc(min).

4.K4S161622D-TC**

5.K4S161622D-TL**

K4S161622D			CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V*2, TA = 0 to 70°C)
Parameter		Value			Unit
Input levels (Vih/Vil)		2.4 / 0.4			V
Input timing measurement reference level		1.4			V
Input rise and fall time		tr / tf = 1 / 1			ns
Output timing measurement reference level		1.4			V
Output load condition		See Fig. 2
	3.3V				Vtt=1.4V

Output

870Ω

1200Ω

50Ω

VOH (DC) = 2.4V, IOH = -2mA

Output

Z0=50Ω

VOL (DC) = 0.4V, IOL = 2mA

50pF*2

50pF*1

	(Fig. 1) DC Output Load Circuit	(Fig. 2) AC Output Load Circuit
Note : 1.	The DC/AC Test Output Load of K4S161622D-55/60/70 is 30pF.
2.	The VDD condition of K4S161622D-55/60	is 3.135V~3.6V.

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

		Parameter		Symbol							Version								Unit	Note
					-55			-60			-70				-80		-10
	CAS Latency			CL	3		2	3		2	3		2	3		2	3	2	CLK
	CLK cycle time			tCC(min)	5.5		-	6		-	7		8.7	8		10	10	12	ns
	Row active to row active delay			tRRD(min)								2							CLK	1
	RAS to CAS delay			tRCD(min)	3		-	3		-	3		2	3		2	2	2	CLK	1
	Row precharge time			tRP(min)	3		-	3		-	3		2	3		2	2	2	CLK	1
	Row active time			tRAS(min)	7		-	7		-	7		5	6		5	5	4	CLK	1
				tRAS(max)							100								us
	Row cycle time			tRC(min)	10		-	10		-	10		7	9		7	7	6	CLK	1
	Last data in to row precharge			tRDL(min)								1							CLK	2, 5
	Last data in to new col.address delay			tCDL(min)								1							CLK	2
	Last data in to burst stop			tBDL(min)								1							CLK	2
	Col. address to col. address delay			tCCD(min)								1							CLK
	Mode Register Set cycle time			tMRS(min)								2							CLK
	Number of valid output data		CAS Latency=3									2							ea	4
			CAS Latency=2									1

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

K4S161622D

CMOS SDRAM

		Parameter	Symbol			Version			Unit
				-55	-60	-70	-80	-10
	CLK cycle time		tCC(min)	5.5	6	7	8	10	ns
	Row active to row active delay		tRRD(min)	11	12	14	16	20	ns
	RAS to CAS delay		tRCD(min)	16.5	18	17.4	20	20	ns
	Row precharge time		tRP(min)	16.5	18	17.4	20	20	ns
	Row active time		tRAS(min)	38.5	42	43.5	48	48	ns
			tRAS(max)			100			us
	Row cycle time		tRC(min)	55	60	60.9	70	70	ns

2.Minimum delay is required to complete write.

3.All parts allow every cycle column address change.

4.In case of row precharge interrupt, auto precharge and read burst stop.

5.Also, supported tRDL=2CLK for - 55/60 part which is distinguished by bucket code "J". From the next generation, tRDL will be only 2CLK for every clock frequency.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter			Symbol		-55			-60		-70		-80		-10		Unit	Note
				Min		Max	Min		Max	Min	Max	Min	Max	Min	Max
CLK cycle time		CAS Latency=3	tCC	5.5		1000	6		1000	7	1000	8	1000	10	1000	ns	1
		CAS Latency=2		-			-			8.7		10		12
CLK to valid		CAS Latency=3	tSAC	-		5	-		5.5	-	5.5	-	6	-	6	ns	1, 2
output delay		CAS Latency=2		-		-	-		-	-	7.7	-	6	-	8
Output data			tOH	2		-	2.5		-	2.5	-	2.5	-	2.5	-	ns	2
CLK high pulse width		CAS Latency=3	tCH	2		-	2.5		-	3	-	3	-	3.5	-	ns	3
		CAS Latency=2		-			-
CLK low pulse width		CAS Latency=3	tCL	2		-	2.5		-	3	-	3	-	3.5	-	ns	3
		CAS Latency=2					-
Input setup time		CAS Latency=3	tSS	1.5		-	1.5		-	1.75	-	2	-	2.5	-	ns	3
		CAS Latency=2		-			-			2.5
Input hold time			tSH	1		-	1		-	1	-	1	-	1	-	ns	3
CLK to output in Low-Z			tSLZ	1		-	1		-	1	-	1	-	1	-	ns	2
CLK to output		CAS Latency=3	tSHZ	-		5	-		5.5	-	5.5	-	6	-	6	ns
in Hi-Z		CAS Latency=2		-		-	-		-	-	7.7	-	6	-	8

Note : 1. Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

K4S161622D

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

A10/AP

A9~ A0

Note

Register

Mode Register Set

H

X

L

L

L

L

X

OP CODE

1, 2

Auto Refresh

H

H

L

L

L

H

X

X

3

Refresh

Entry

L

3

Self

L

H

H

H

3

Refresh

Exit

L

H

X

X

H

X

X

X

3

Bank Active & Row Addr.

H

X

L

L

H

H

X

V

Row Address

Read &

Auto Precharge Disable

H

X

L

H

L

H

X

V

L

Column

4

Column Address

Address

Auto Precharge Enable

H

(A0~A7)

4, 5

Write &

Auto Precharge Disable

H

X

L

H

L

L

X

V

L

Column

4

Column Address

Address

Auto Precharge Enable

H

(A0~A7)

4, 5

Burst Stop

H

X

L

H

H

L

X

X

6

Precharge

Bank Selection

H

X

L

L

H

L

X

V

L

X

Both Banks

X

H

Entry

H

L

H

X

X

X

X

Clock Suspend or

X

L

V

V

V

Active Power Down

Exit

L

H

X

X

X

X

X

Entry

H

L

H

X

X

X

X

Precharge Power Down Mode

L

H

H

H

X

Exit

L

H

H

X

X

X

X

L

V

V

V

DQM

H

X

V

X

7

No Operation Command

H

X

H

X

X

X

X

X

L

H

H

H

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Note : 1. OP Code : Operand Code

A0 ~ A10/AP, BA : Program keys. (@MRS)

2.MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state.

4.BA : Bank select address.

If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected.

If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the assoiated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

K4S161622D																								CMOS SDRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address		BA			A10/AP		A9			A8		A7		A6			A5		A4	A3				A2		A1		A0
Function		RFU			RFU		W.B.L				TM					CAS Latency				BT					Burst Length
		Test Mode								CAS Latency							Burst Type							Burst Length
A8		A7			Type			A6		A5		A4	Latency				A3		Type	A2		A1		A0		BT = 0		BT = 1
0		0		Mode Register Set				0		0	0		Reserved			0		Sequential		0		0		0	1		1
0		1			Reserved			0		0	1		-			1		Interleave		0		0		1	2		2
1		0			Reserved			0		1	0		2							0		1		0	4		4
1		1			Reserved			0		1	1		3							0		1		1	8		8
		Write Burst Length						1		0	0		Reserved							1		0		0	Reserved		Reserved
A9				Length				1		0	1		Reserved							1		0		1	Reserved		Reserved
0				Burst				1		1	0		Reserved							1		1		0	Reserved		Reserved
1				Single Bit				1		1	1		Reserved							1		1		1	Full Page		Reserved
																			Full Page Length : x4 (1024), x8 (512), x16 (256)

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1.Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.

K4S161622D									CMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address			Sequential						Interleave
A1	A0
0	0	0	1		2	3	0	1		2	3
0	1	1	2		3	0	1	0		3	2
1	0	2	3		0	1	2	3		0	1
1	1	3	0		1	2	3	2		1	0

BURST SEQUENCE (BURST LENGTH = 8)

	Initial Address								Sequential								Interleave
A2		A1		A0
0		0		0		0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
0		0		1		1	2	3	4	5	6	7	0	1	0	3	2	5	4	7	6
0		1		0		2	3	4	5	6	7	0	1	2	3	0	1	6	7	4	5
0		1		1		3	4	5	6	7	0	1	2	3	2	1	0	7	6	5	4
1		0		0		4	5	6	7	0	1	2	3	4	5	6	7	0	1	2	3
1		0		1		5	6	7	0	1	2	3	4	5	4	7	6	1	0	3	2
1		1		0		6	7	0	1	2	3	4	5	6	7	4	5	2	3	0	1
1		1		1		7	0	1	2	3	4	5	6	7	6	5	4	3	2	1	0

K4S161622D

CMOS SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.

BANK ADDRESS (BA)

: In case x 4

This SDRAM is organized as two independent banks of 2,097,152 words x 4 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations.

: In case x 8

This SDRAM is organized as two independent banks of 1,048,576 words x 8 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations.

: In case x 16

This SDRAM is organized as two independent banks of 524,288 words x 16 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations.

ADDRESS INPUTS (A0 ~ A10/AP)

: In case x 4

The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA during read or write command.

: In case x 8

The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA during read or write command.

: In case x 16

The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10/

AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA during read or write command.

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1.Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for both banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

K4S161622D

CMOS SDRAM

DEVICE OPERATIONS (Continued)

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS,

RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A10/AP and BA in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) uses A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP and BA. The write burst length is programmed using A9. A7 ~ A8, A10/AP, BA must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of two banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before the other bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be

active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification.

BURST READ

The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also.

K4S161622D

CMOS SDRAM

DEVICE OPERATIONS (Continued)

DQM OPERATION

The DQM is used to mask input and output operations. It works

similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also.

PRECHARGE

The precharge operation is performed on an active bank by

asserting low on CS, RAS, WE and A10/AP with valid BA of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank active command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when both banks are in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy

tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state.

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after performing precharge to all the banks, both banks are in idle state.

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with clock cycle time and them rounding up to the next higher integer.

The auto refresh command must be followed by NOP's until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms.

SELF REFRESH

The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption.

The self refresh mode is entered from both banks idle state by

asserting low on CS, RAS, CAS and CKE with high on WE. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode.

The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting in self refresh mode.

K4S161622D

CMOS SDRAM

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1)

Clock Suspended During Write (BL=4)

2) Clock Suspended During Read (BL=4)

CLK

CMD

WR

RD

CKE

Masked by CKE

Masked by CKE

Internal

CKE

D0

DQ(CL2)

D0

D1

D2

D3

Q0

Q1

Q2

Q3

DQ(CL3)

D0

D1

D2

D3

Q0

Q1

Q2

Q3

Not Written

Suspended Dout

2. DQM Operation

1) Write Mask (BL=4)

2) Read Mask (BL=4)

CLK

CMD	WR		RD

DQM

Masked by DQM

DQ(CL2) D0D1D3

DQ(CL3) D0D1D3

DQM to Data-in Mask = 0

3) DQM with Clock Suspended (Full Page Read) Note 2

CLK

Masked by DQM

Hi-Z

Q0 Q2Q3

Hi-Z	Q1	Q2	Q3

DQM to Data-out Mask = 2

CMD

RD

CKE

DQM

DQ(CL2)

Hi-Z

Hi-Z

Hi-Z

Q0

Q2

Q4

Q6

Q7

Q8

Hi-Z

Hi-Z

Hi-Z

DQ(CL3)

Q1

Q3

Q5

Q6

Q7

*Note : 1. CKE to CLK disable/enable = 1CLK.

2.DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3.DQM masks both data-in and data-out.