Samsung K4S560832C-TC-L1L, K4S560832C-TC-L1H, K4S560832C-TC-L7C, K4S560832C-TC-L75 Datasheet

K4S560832C

CMOS SDRAM

256Mbit SDRAM

8M x 8bit x 4 Banks Synchronous DRAM LVTTL

Revision 0.1

Sept. 2001

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Sept. 2001

K4S560832C

CMOS SDRAM

Revision History

Revision 0.0 (Mar. 06, 2001)

Revision 0.1 (Sep. 06, 2001)

•Redefined IDD1 & IDD4 in DC Characteristics

•Changed the Notes in Operating AC Parameter.

<Before >

5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

<After >

5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 0.1 Sept. 2001

K4S560832C

CMOS SDRAM

8M x 8Bit x 4 Banks Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

• JEDEC standard 3.3V power supply

The K4S560832C is 268,435,456 bits synchronous high data rate

•

LVTTL compatible with multiplexed address

Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabri-

•

Four banks operation

cated with SAMSUNG's high performance CMOS technology. Syn-

• MRS cycle with address key programs

chronous design allows precise cycle control with the use of

-. CAS latency (2 & 3)

system clock I/O transactions are possible on every clock cycle.

-. Burst length (1, 2, 4, 8 & Full page)

Range of operating frequencies, programmable burst length and

-. Burst type (Sequential & Interleave)

programmable latencies allow the same device to be useful for a

• All inputs are sampled at the positive going edge of the system

variety of high bandwidth, high performance memory system appli-

clock.

cations.

• Burst read single-bit write operation

ORDERING INFORMATION

•

DQM for masking

•

Auto & self refresh

Part No.

Max Freq.

Interface

Package

•

64ms refresh period (8K Cycle)

K4S560832C-TC/L7C

133MHz(CL=2)

K4S560832C-TC/L75

133MHz(CL=3)

LVTTL

54pin

TSOP(II)

K4S560832C-TC/L1H

100MHz(CL=2)

K4S560832C-TC/L1L

100MHz(CL=3)

FUNCTIONAL BLOCK DIAGRAM

I/O

LWE

Data Input Register

Control

LDQM

Bank Select

	Address		CounterRefresh	BufferRow	DecoderRow			8M x 8	AMPSense	BufferOutput
								8M x 8			DQi
								8M x 8
CLK								8M x 8
	Register		LRAS	LCBR	Buffer.Col
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR		LDQM
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Sept. 2001

K4S560832C

CMOS SDRAM

PIN CONFIGURATION (Top view)

	VDD				1	54		VSS
	DQ0				2	53		DQ7
VDDQ					3	52		VSSQ
	N.C				4	51		N.C
	DQ1				5	50		DQ6
VSSQ					6	49		VDDQ
	N.C				7	48		N.C
	DQ2				8	47		DQ5
VDDQ					9	46		VSSQ
	N.C				10	45		N.C
	DQ3				11	44		DQ4
VSSQ					12	43		VDDQ
	N.C				13	42		N.C
	VDD				14	41		VSS
		N.C			15	40		N.C/RFU
		WE			16	39		DQM
	CAS				17	38		CLK
	RAS				18	37		CKE
		CS			19	36		A12
	BA0				20	35		A11
	BA1				21	34		A9
A10/AP					22	33		A8
		A0			23	32		A7
		A1			24	31		A6
		A2			25	30		A5
		A3			26	29		A4
	VDD				27	28		VSS

54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitcH)

PIN FUNCTION DESCRIPTION

			Pin			Name	Input Function
	CLK				System clock		Active on the positive going edge to sample all inputs.
							Disables or enables device operation by masking or enabling all inputs except
	CS				Chip select
							CLK, CKE and DQM
							Masks system clock to freeze operation from the next clock cycle.
	CKE				Clock enable		CKE should be enabled at least one cycle prior to new command.
							Disable input buffers for power down in standby.
	A0 ~ A12				Address		Row/column addresses are multiplexed on the same pins.
							Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
	BA0 ~ BA1				Bank select address		Selects bank to be activated during row address latch time.
							Selects bank for read/write during column address latch time.
							Latches row addresses on the positive going edge of the CLK with RAS low.
	RAS				Row address strobe
							Enables row access & precharge.
							Latches column addresses on the positive going edge of the CLK with CAS low.
	CAS				Column address strobe
							Enables column access.
							Enables write operation and row precharge.
	WE				Write enable
							Latches data in starting from CAS, WE active.
	DQM				Data input/output mask		Makes data output Hi-Z, tSHZ after the clock and masks the output.
							Blocks data input when DQM active.
	DQ0 ~7				Data input/output		Data inputs/outputs are multiplexed on the same pins.
	VDD/VSS				Power supply/ground		Power and ground for the input buffers and the core logic.
	VDDQ/VSSQ				Data output power/ground		Isolated power supply and ground for the output buffers to provide improved noise
							immunity.
	N.C/RFU				No connection		This pin is recommended to be left No Connection on the device.
					/reserved for future use
							Rev. 0.1 Sept. 2001