Samsung K4S561632E-NCL60, K4S561632E-NC75, K4S561632E-NC60, K4S560832E-NCL75, K4S560832E-NC75 Datasheet

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

256Mb E-die SDRAM Specification

54pin sTSOP-II

Revision 1.0

August. 2003

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.0 August, 2003

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

Revision History

Revision 1.0 (August. 2003)

- First release.

Rev. 1.0 August, 2003

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM

FEATURES

•JEDEC standard 3.3V power supply

•LVTTL compatible with multiplexed address

•Four banks operation

•MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

•All inputs are sampled at the positive going edge of the system clock.

•Burst read single-bit write operation

•DQM (x4,x8) & L(U)DQM (x16) for masking

•Auto & self refresh

•64ms refresh period (8K Cycle)

GENERAL DESCRIPTION

The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Ordering Information

Part No.	Orgainization	Max Freq.	Interface	Package
K4S560432E-NC(L)75	64M x 4	133MHz	LVTTL	54pin sTSOP
K4S560832E-NC(L)75	32M x 8	133MHz	LVTTL	54pin sTSOP
K4S561632E-NC(L)60/75	16M x 16	166/133MHz	LVTTL	54pin sTSOP

Organization	Row Address	Column Address
64Mx4	A0~A12	A0-A9, A11
32Mx8	A0~A12	A0-A9
16Mx16	A0~A12	A0-A8

Row & Column address configuration

Rev. 1.0 August, 2003

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

Package Physical Dimension

54pin sTSOP(II)-300

Units : Millimeters

															(2-R 0.15)
						#54						#28
															(0.80)
								( 2.00 Dp0~0.05 BTM)
						(1.00)						7.6
		(1.00)
						#1						#27			(0.80)	0.125	+0.075-0.035
0.665±0.05 0.210±0.05							14.40MAX					0.051.00±	1.20MAX	(1.10)	0.10 MAX
							(14.20)
	(
	2										(14°)
		-					14.00±0.10
			R	0
				.
					1
					5
						)
				0)		(0.50)	0.50TYP			0.20	+0.075
	-R		.3								-0.035	MIN
		0					0.50±0.05
	(2						[	0.07 MAX	]		(14°)	0.05
NOTE
1. (			) IS REFERENCE
2. [			] IS ASS’Y OUT QUALITY

(0.50)			(2-R 0.30)

											(8.22)				9.22±0.20
								(14°)
											(0.50)												0.40~0.60
	1	°	)																			.25)
(		4														0
																			(R
								.	2	5	)
				( R		0																0.25TYP
															0×				~8×

Rev. 1.0 August, 2003

SDRAM 256Mb E-die (x4, x8, x16)

CMOS SDRAM

FUNCTIONAL BLOCK DIAGRAM

Data Input Register

Bank Select

			Counter Refresh		Decoder Row		16M x 4 / 8M x 8 / 4M x 16	AMP Sense
				Buffer Row			16M x 4 / 8M x 8 / 4M x 16
CLK	Address						16M x 4 / 8M x 8 / 4M x 16
							16M x 4 / 8M x 8 / 4M x 16
ADD	Register
			LRAS	LCBR	Buffer .Col		Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS	LWCBR
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE

	I/O					LWE
	Control					LDQM
	Output					DQi
	Buffer

LDQM

L(U)DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.0 August, 2003