K4R271669A/K4R441869A |
Direct RDRAM™ |
128/144Mbit RDRAM
256K x 16/18 bit x 2*16 Dependent Banks
Direct RDRAMTM
Revision 1.02
January 2000
Page -1 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Revision History
Version 1.0 (July 1999) - Preliminary
- Based on the Rambus Datasheet 1.0 ver.
Version 1.01 (October 1999)
On page 1
-Delete the part numbers of low power
On page 32
-Add the data of CNFGA Register @ Figure 28
On page 33
-Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register
On page 44
-Add the Tj value from TBD to Max. 100°C @ Table 18
On page 46
- Add the ΘJC value from TBD to 0.2°C/Watt @ Table 20
On page 55
- Add the current values for 356MHz and 300MHz RDRAM device
Version 1.02 (January 2000)
* Change the part number of RDRAM Component according to New Code System since ’00.Jan.1st
On page 45
-Reduce swing of VIH,CMOS & VIL,CMOS from “0.5VCMOS±0.6V“to “0.5VCMOS±0.4V“
-Relax tS1 from 1.0ns to “1.25ns“( But, Keep tH1 as 1.0ns)
Page 0 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Overview
The Rambus Direct RDRAM™ is a general purpose highperformance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.
The 128/144Mbit Direct Rambus DRAMs (RDRAMâ) are extremely high-speed CMOS DRAMs organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage and bandwidth or for error correction.
Features
♦Highest sustained bandwidth per DRAM device
-1.6GB/s sustained data transfer rate
-Separate control and data buses for maximized efficiency
-Separate row and column control buses for easy scheduling and highest performance
-32 banks: four transactions can take place simultaneously at full bandwidth data rates
♦Low latency features
-Write buffer to reduce read latency
-3 precharge mechanisms for controller flexibility
-Interleaved transactions
♦Advanced power management:
-Direct RDRAM operates from a 2.5 volt supply
-Multiple low power states allows flexibility in power consumption versus time to transition to active state
-Power-down self-refresh
♦Organization: 1Kbyte pages and 32 banks, x 16/18
-x18 organization allows ECC configurations or increased storage/bandwidth
-x16 organization for low cost applications
♦Uses Rambus Signaling Level (RSL) for up to 800MHz operation
SAMSUNG 001
K4Rxxxx69A-Nxxx
a. Normal Package
SAMSUNG 001
K4Rxxxx69A-Mxxx
M
b. Mirrored Package
Figure 1: Direct RDRAM CSP Package
The 128/144Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as well as lowprofile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
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Speed |
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Organization |
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Part Number |
Bin |
I/O |
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tRAC (Row |
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Freq. |
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Access |
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MHz |
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Time) ns |
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256Kx16x32sa |
-CG6 |
600 |
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53.3 |
K4R271669A-Nb(M)CcG6 |
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-CK7 |
711 |
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45 |
K4R271669A-N(M)CK7 |
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-CK8 |
800 |
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45 |
K4R271669A-N(M)CK8 |
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256Kx18x32s |
-CG6 |
600 |
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53.3 |
K4R441869A-N(M)CG6 |
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-CK7 |
711 |
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45 |
K4R441869A-N(M)CK7 |
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-CK8 |
800 |
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45 |
K4R441869A-N(M)CK8 |
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a.The “32s"designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture.
b.The “N“designator indicates the normal package and the “M“indicates the mirrored package.
c.The “C“designator indicates that this RDRAM core uses Normal Power Self Refresh.
Page 1 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Pinouts and Definitions
Normal Package
This table shows the pin assignments of the normal RDRAM package.
Table 1 : a. Center-Bonded Device(Top View For Normal Package) |
b. Top marking example of normal package |
12 |
GND |
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VDD |
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VDD |
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GND |
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11 |
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10 |
DQA7 |
DQA4 |
CFM |
CFMN |
RQ5 |
RQ3 |
DQB0 |
DQB4 |
DQB7 |
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9 |
GND |
VDD |
GND |
GNDa |
VDD |
GND |
VDD |
VDD |
GND |
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8 |
CMD |
DQA5 |
DQA2 |
VDDa |
RQ6 |
RQ2 |
DQB1 |
DQB5 |
SIO1 |
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7 |
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6 |
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5 |
SCK |
DQA6 |
DQA1 |
VREF |
RQ7 |
RQ1 |
DQB2 |
DQB6 |
SIO0 |
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4 |
VCMOS |
GND |
VDD |
GND |
GND |
VDD |
GND |
GND |
VCMOS |
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3 |
DQA8* |
DQA3 |
DQA0 |
CTMN |
CTM |
RQ4 |
RQ0 |
DQB3 |
DQB8* |
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2 |
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1 |
GND |
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VDD |
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VDD |
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GND |
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A |
B |
C |
D |
E |
F |
G |
H |
J |
ROW
SAMSUNG 001
K4Rxxxx69A-Nxxx
For normal package, pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 position is marked by the marker “ “.
Top View
COL
Mirrored Package
Chip |
This table shows the pin assignments of the mirrored RDRAM package.
Table 2: a.Center-Bonded Device(Top View For Mirrored Package)
12 |
GND |
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VDD |
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VDD |
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GND |
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11 |
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10 |
DQA8* |
DQA3 |
DQA0 |
CTMN |
CTM |
RQ4 |
RQ0 |
DQB3 |
DQB8* |
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9 |
VCMOS |
GND |
VDD |
GND |
GND |
VDD |
GND |
GND |
VCMOS |
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8 |
SCK |
DQA6 |
DQA1 |
VREF |
RQ7 |
RQ1 |
DQB2 |
DQB6 |
SIO0 |
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7 |
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6 |
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5 |
CMD |
DQA5 |
DQA2 |
VDDa |
RQ6 |
RQ2 |
DQB1 |
DQB5 |
SIO1 |
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4 |
GND |
VDD |
GND |
GNDa |
VDD |
GND |
VDD |
VDD |
GND |
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3 |
DQA7 |
DQA4 |
CFM |
CFMN |
RQ5 |
RQ3 |
DQB0 |
DQB4 |
DQB7 |
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2 |
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1 |
GND |
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VDD |
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VDD |
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GND |
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A |
B |
C |
D |
E |
F |
G |
H |
J |
ROW
*DQA8/DQB8 are just used for 144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb RDRAM.
b.Top marking example of mirrored package
SAMSUNG 001
K4Rxxxx69A-Mxxx
M
For mirrored package, pin #1(ROW 1, COL A) is located at the A1 postion on the top side and the A1 position is marked by the alphabet “M“.
COL
Page 2 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Table 3: Pin Description
Signal |
I/O |
Type |
# of Pins |
Description |
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SIO1,SIO0 |
I/O |
CMOSa |
2 |
Serial input/output. Pins for reading from and writing to the control |
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registers using a serial access protocol. Also used for power man- |
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agement. |
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CMD |
I |
CMOSa |
1 |
Command input. Pins used in conjunction with SIO0 and SIO1 for |
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reading from and writing to the control registers. Also used for |
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power management. |
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SCK |
I |
CMOSa |
1 |
Serial clock input. Clock source used for reading from and writing to |
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the control registers |
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VDD |
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10 |
Supply voltage for the RDRAM core and interface logic. |
VDDa |
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1 |
Supply voltage for the RDRAM analog circuitry. |
VCMOS |
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2 |
Supply voltage for CMOS input/output pins. |
GND |
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13 |
Ground reference for RDRAM core and interface. |
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GNDa |
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1 |
Ground reference for RDRAM analog circuitry. |
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DQA8..DQA0 |
I/O |
RSLb |
9 |
Data byte A. Nine pins which carry a byte of read or write data |
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between the Channel and the RDRAM. DQA8 is not used by |
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RDRAMs with a x16 organization. |
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CFM |
I |
RSLb |
1 |
Clock from master. Interface clock used for receiving RSL signals |
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from the Channel. Positive polarity. |
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CFMN |
I |
RSLb |
1 |
Clock from master. Interface clock used for receiving RSL signals |
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from the Channel. Negative polarity |
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VREF |
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1 |
Logic threshold reference voltage for RSL signals |
CTMN |
I |
RSLb |
1 |
Clock to master. Interface clock used for transmitting RSL signals |
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to the Channel. Negative polarity. |
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CTM |
I |
RSLb |
1 |
Clock to master. Interface clock used for transmitting RSL signals |
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to the Channel. Positive polarity. |
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RQ7..RQ5 or |
I |
RSLb |
3 |
Row access control. Three pins containing control and address |
ROW2..ROW0 |
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information for row accesses. |
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RQ4..RQ0 or |
I |
RSLb |
5 |
Column access control. Five pins containing control and address |
COL4..COL0 |
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information for column accesses. |
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DQB8.. |
I/O |
RSLb |
9 |
Data byte B. Nine pins which carry a byte of read or write data |
DQB0 |
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between the Channel and the RDRAM. DQB8 is not used by |
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RDRAMs with a x16 organization. |
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Total pin count per package |
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62 |
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a.All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b.All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
DQB8..DQB0 |
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RQ7..RQ5 or |
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CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN |
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RQ4..RQ0 or |
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DQA8..DQA |
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ROW2..ROW0 |
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COL4..COL0 |
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9 |
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3 |
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2 |
2 |
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5 |
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9 |
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RCLK |
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RCLK |
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1:8 Demux |
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1:8 Demux |
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TCLK |
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RCLK |
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Packet Decode |
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Control Registers |
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Packet Decode |
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ROWR |
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ROWA |
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COLX |
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COLC |
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COLM |
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11 |
5 |
5 |
9 |
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6 |
5 |
5 |
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5 |
5 |
5 |
6 |
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8 |
8 |
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ROP DR |
BR |
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R |
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REFR |
Power Modes DEVID |
XOP DX |
BX COP DC |
BC |
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C |
MB MA |
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AV |
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M |
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S |
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Match |
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Mux |
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Match |
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Match |
Write |
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DM |
Row Decode |
PRER |
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XOP Decode |
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Buffer |
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PREX |
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ACT |
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Mux |
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Mux |
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Column Decode & Mask |
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Sense Amp |
DRAM Core |
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PREC |
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RD, WR |
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32x72 |
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32x72 |
512x64x144 |
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32x72 |
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72 |
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SAmp |
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SAmp |
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Internal DQB Data Path |
72 |
0 |
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Bank 0 |
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0 |
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Internal DQA Data Path |
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SAmp |
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SAmp |
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72 |
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0/1 |
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Bank 1 |
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0/1 |
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72 |
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SAmp |
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SAmp |
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1/2 |
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Bank 2 |
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1/2 |
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RCLK |
9 |
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9 |
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9 |
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9 |
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RCLK |
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••• |
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••• |
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••• |
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SAmp SAmp SAmp |
15 14/15 13/14 |
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Bank 13 |
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15 14/15 13/14 |
SAmp SAmp SAmp |
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9 |
1:8 Demux |
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Write Buffer |
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Bank 14 |
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Buffer Write |
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Demux 1:8 |
9 |
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Bank 15 |
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SAmp |
16 |
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Bank 16 |
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16 |
SAmp |
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SAmp SAmp |
17/18 16/17 |
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17/18 16/17 |
SAmp SAmp |
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TCLK |
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9 |
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9 |
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TCLK |
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Bank 17 |
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Bank 18 |
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9 |
Mux |
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••• |
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••• |
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••• |
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8:1 |
9 |
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8:1 |
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SAmp |
29/30 |
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Bank 29 |
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29/30 |
SAmp |
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Mux |
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Bank 30 |
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SAmp |
30/31 |
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30/31 |
SAmp |
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Bank 31 |
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Figure 2: 128/144 Mbit Direct RDRAM Block Diagram
Page 4 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
General Description
Figure 2 is a block diagram of the 128/144 Mbit Direct RDRAM. It consists of two major blocks: a “core“block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6GB/s.
Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure 2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel.
Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From- Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi- plexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the RDRAM.
Banks: The 16Mbyte core of the RDRAM is divided into 32 0.5Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed.
Sense Amps: The RDRAM contains 34 sense amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed.
RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a
24-bit ROWA (row-activate) or ROWR (row-operation) packet.
COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multi- plexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.
ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.
RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround.
PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge.
PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.
Page 5 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Packet Format
Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 4 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the “RsvX” notation to reserve bits for future address field extension.
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Table 4: Field Description for ROWA Packet and ROWR Packet |
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Field |
Description |
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DR4T,DR4F |
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. |
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DR3..DR0 |
Device address for ROWA or ROWR packet. |
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BR4..BR0 |
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. |
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AV |
Selects between ROWA packet (AV=1) and ROWR packet (AV=0). |
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R8..R0 |
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM. |
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ROP10..ROP0 |
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions. |
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Figure 3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 5 describes the fields which comprise these packets.
The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit.
The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time tRTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet.
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Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet |
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Field |
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Description |
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S |
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Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. |
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DC4..DC0 |
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Device address for COLC packet. |
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BC4..BC0 |
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Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s). |
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C5..C0 |
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Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. |
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COP3..COP0 |
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Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. |
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M |
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Selects between COLM packet (M=1) and COLX packet (M=0). |
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MA7..MA0 |
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Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0. |
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MB7..MB0 |
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Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0. |
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DX4..DX0 |
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Device address for COLX packet. |
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BX4..BX0 |
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Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s). |
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XOP4..XOP0 |
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Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions. |
Page 6 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
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T0 |
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T1 |
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T2 |
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T3 |
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T8 |
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T9 |
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T11 |
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DR4T DR2 |
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BR0 |
BR3 |
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RsvR |
R8 |
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R5 |
R2 |
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DR4T DR2 |
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BR0 |
BR3 |
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ROP10 ROP8 |
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ROP5 ROP2 |
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DR4F DR1 |
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BR1 |
BR4 |
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RsvR |
R7 |
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R4 |
R1 |
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DR4F DR1 |
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BR1 |
BR4 |
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ROP9 ROP7 |
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ROP4 ROP1 |
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DR3 DR0 |
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BR2 |
RsvB |
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AV=1 |
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R3 |
R0 |
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BR2 |
RsvB |
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AV=0 |
ROP6 |
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ROWA Packet |
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ROWR Packet |
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T0 |
T1 |
T2 |
T3 |
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CTM/CFM |
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COL4 |
DC4 |
S=1 |
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RsvC |
C4 |
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COL3 |
DC3 |
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C5 |
C3 |
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COL2 |
DC2 COP1 |
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RsvB |
BC2 |
C2 |
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COL1 |
DC1 COP0 |
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BC4 |
BC1 |
C1 |
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COL0 |
DC0 COP2 |
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COP3 BC3 |
BC0 |
C0 |
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COLC Packet |
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T8 |
T9 |
T10 |
T11 |
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CTM/CFM |
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COL4 |
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S=1a |
MA7 MA5 MA3 MA1 |
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COL3 |
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M=1 MA6 MA4 MA2 MA0 |
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COL2 |
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MB7 MB4 MB1 |
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COL1 |
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MB6 MB3 MB0 |
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COL0 |
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MB5 MB2 |
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a The COLM is associated with a |
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previous COLC, and is aligned |
COLM Packet |
with the present COLC, indicated |
by the Start bit (S=1) position.
Figure 3:
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CTM/CFM |
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ROW2 |
ACT a0 |
PRER c0 |
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..ROW0 |
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COL4 |
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tPACKET |
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WR b1 |
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..COL0 |
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MSK (b1) |
PREX d0 |
DQA8..0 |
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DQB8..0 |
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T12 |
T13 |
T14 |
T15 |
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CTM/CFM |
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COL4 |
S=1b |
DX4 XOP4 RsvB |
BX1 |
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COL3 |
M=0 |
DX3 XOP3 BX4 |
BX0 |
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COL2 |
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DX2 XOP2 BX3 |
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COL1 |
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DX1 XOP1 BX2 |
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COL0 |
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DX0 XOP0 |
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b The COLX is aligned |
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COLX Packet |
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with the present COLC, |
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indicated by the Start |
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bit (S=1) position. |
Packet Formats
Page 7 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Field Encoding Summary
Table 6 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a
broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed.
Table 6: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T |
DR4F |
Device Selection |
Device Match signal (DM) |
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1 |
1 |
All devices (broadcast) |
DM is set to 1 |
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0 |
1 |
One device selected |
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 |
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1 |
0 |
One device selected |
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 |
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0 |
0 |
No packet present |
DM is set to 0 |
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Table 7 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps.
An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-acti- vate) command is similar to the ACT command, except the
row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in “Power state management “on page 38. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in “Current and Temperature Control“on page 43.
Table 7: ROWA Packet and ROWR Packet Field Encodings
DMa |
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ROP10..ROP0 Field |
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Command Description |
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AV |
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Name |
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10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2:0 |
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0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
--- |
- |
No operation. |
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1 |
1 |
Row address |
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ACT |
Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb. |
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1 |
0 |
1 |
1 |
0 |
0 |
0 |
xc |
x |
x |
000 |
PRER |
Precharge bank BR4..BR0 of this device. |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
x |
000 |
REFA |
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device. |
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Increment REFR if BR4..BR0 = 1111 (see Figure 50). |
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1 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
x |
000 |
REFP |
Precharge bank BR4..BR0 of this device after REFA (see Figure 50). |
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1 |
0 |
x |
x |
0 |
0 |
0 |
0 |
1 |
x |
000 |
PDNR |
Move this device into the powerdown (PDN) power state (see Figure 47). |
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1 |
0 |
x |
x |
0 |
0 |
0 |
1 |
0 |
x |
000 |
NAPR |
Move this device into the nap (NAP) power state (see Figure 47). |
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1 |
0 |
x |
x |
0 |
0 |
0 |
1 |
1 |
x |
000 |
NAPRC |
Move this device into the nap (NAP) power state conditionally |
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0 |
x |
x |
x |
x |
x |
x |
x |
0 |
000 |
ATTNb |
Move this device into the attention (ATTN) power state (see Figure 45). |
1 |
0 |
x |
x |
x |
x |
x |
x |
x |
1 |
000 |
RLXR |
Move this device into the standby (STBY) power state (see Figure 46). |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
x |
001 |
TCAL |
Temperature calibrate this device (see Figure 52). |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
x |
010 |
TCEN |
Temperature calibrate/enable this device (see Figure 52). |
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1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
000 |
NOROP |
No operation. |
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a.The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 6.
b.The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c.An “x“entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
Page 8 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Table 8 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 17 for a more detailed description.
The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See “Power State Management “on page 38.
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Table 8: COLC Packet Field Encodings |
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S |
DC4.. DC0 |
COP3..0 |
Name |
Command Description |
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(select device)a |
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0 |
---- |
----- |
- |
No operation. |
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1 |
/= (DEVID4 ..0) |
----- |
- |
Retire write buffer of this device. |
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1 |
== (DEVID4 ..0) |
x000b |
NOCOP |
Retire write buffer of this device. |
1 |
== (DEVID4 ..0) |
x001 |
WR |
Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer. |
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1 |
== (DEVID4 ..0) |
x010 |
RSRV |
Reserved, no operation. |
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1 |
== (DEVID4 ..0) |
x011 |
RD |
Read column C5..C0 of bank BC4..BC0 of this device. |
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1 |
== (DEVID4 ..0) |
x100 |
PREC |
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 14). |
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1 |
== (DEVID4 ..0) |
x101 |
WRA |
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. |
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1 |
== (DEVID4 ..0) |
x110 |
RSRV |
Reserved, no operation. |
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1 |
== (DEVID4 ..0) |
x111 |
RDA |
Same as RD, but precharge bank BC4..BC0 afterward. |
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1 |
== (DEVID4 ..0) |
1xxx |
RLXC |
Move this device into the standby (STBY) power state (see Figure 46). |
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a.“/= “means not equal, “== “means equal.
b.An “x“entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value(1001).
Table 9 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see “Current and Temperature Control“on page 43), and for the RLXX power mode command (see “Power State Management“on page 38).
Table 9: COLM Packet and COLX Packet Field Encodings
M |
DX4 .. DX0 |
XOP4..0 |
Name |
Command Description |
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(selects device) |
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1 |
---- |
- |
MSK |
MB/MA bytemasks used by WR/WRA. |
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0 |
/= (DEVID4 ..0) |
- |
- |
No operation. |
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0 |
== (DEVID4 ..0) |
00000 |
NOXOP |
No operation. |
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0 |
== (DEVID4 ..0) |
1xxx0a |
PREX |
Precharge bank BX4..BX0 of this device (see Figure 14). |
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0 |
== (DEVID4 ..0) |
x10x0 |
CAL |
Calibrate (drive) IOL current for this device (see Figure 51). |
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0 |
== (DEVID4 ..0) |
x11x0 |
CAL/SAM |
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 51). |
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0 |
== (DEVID4 ..0) |
xxx10 |
RLXX |
Move this device into the standby (STBY) power state (see Figure 46). |
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0 |
== (DEVID4 ..0) |
xxxx1 |
RSRV |
Reserved, no operation. |
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a. An “x“entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
DQ Packet Timing
Figure 4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point.
An RD or RDA command will transmit a dualoct of read data Q a time tCAC later. This time includes one to five cycles of round-trip propagation delay on the Channel. The
tCAC parameter may be programmed to a one of a range of values ( 8, 9, 10, 11, or 12 tCYCLE). The value chosen depends upon the number of RDRAM devices on the
Channel and the RDRAM timing bin. See Figure 39 for more information.
A WR or WRA command will receive a dualoct of write data D a time tCWD later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction.
When a Q packet follows a D packet (shown in the left half of the figure), a gap (tCAC -tCWD) will automatically appear between them because the tCWD value is always less than the tCAC value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets.
When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the
tCWD value is less than the tCAC value. However, , a gap of tCAC -tCWD or greater must be inserted between the COLC
packets with the RD WR commands by the controller so the Q and D packets do not overlap.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
This gap on the DQA/DQB pins appears automatically |
This gap on the COL pins must be inserted by the controller |
ROW2 |
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tCAC -tCWD |
tCAC-tCWD |
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..ROW0 |
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WR d1 |
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• • • |
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tCWD |
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WR d1 |
tCWD |
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• • • |
WR d1 |
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WR d1 |
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COL4 |
WR a1 |
RD b1 |
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WR d1 |
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RD c1 |
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• • • |
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..COL0 |
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Q (b1) |
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Q (c1) |
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Q (b1) |
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Q (c1) |
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Q (a1) |
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Q (c1) |
D |
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Q (a1) |
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Q (c1) |
D (d1) |
DQA8..0 |
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Q (a1) |
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Q (a1) |
D (d1) |
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D (a1) |
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DQB8..0 |
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tCAC |
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• • • |
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• • • |
tCAC |
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Figure 4: Read (Q) and Write (D) Data Packet - Timing for tCAC = 8, 9, 10, 11, or 12 tCYCLE
COLM Packet to D Packet Mapping
Figure 5 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time tRTR after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure 17 for more details.
If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (tRTR after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a
housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits).
Figure 5 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0).
Page 10 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
ROW2 |
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ACT a0 |
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PRER a2 |
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ACT b0 |
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COL4 |
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WR a1 |
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tRTR |
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retire (a1) |
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..COL0 |
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MSK (a1) |
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DQA8..0 |
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tCWD |
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D (a1) |
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DQB8..0 |
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Transaction a: WR |
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a0 = {Da,Ba,Ra} |
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a1 = {Da,Ba,Ca1} |
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a3 = {Da,Ba} |
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COLM Packet |
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D Packet |
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T17 |
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T19 |
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CTM/CFM |
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COL4 MA7 MA5 MA3 MA1
COL3 |
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M=1 |
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MA6 MA4 |
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MA2 MA0 |
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COL2 MB7 MB4 MB1
COL1 MB6 MB3 MB0
COL0 MB5 MB2
Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one.
When M=1, the MA and MB fields control writing of individual data bytes.
When M=0, all data bytes are written unconditionally.
DQB8
DQB7
••• DQB1
DQB0
DQA8
DQA7
DB8 DB17 DB26 DB35 DB45 DB53 DB62 DB71
DB7 DB16 DB25 DB34 DB44 DB52 DB61 DB70
DB1 |
DB10 |
DB19 |
DB28 |
DB37 |
DB46 |
DB55 |
DB64 |
DB0 |
DB9 |
DB18 DB27 DB36 DB45 DB54 DB63 |
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MB0 |
MB1 |
MB2 MB3 MB4 MB5 MB6 MB7 |
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DA8 |
DA17 |
DA26 |
DA35 |
DA45 |
DA53 |
DA62 |
DA71 |
DA7 |
DA16 |
DA25 |
DA34 |
DA44 |
DA52 |
DA61 |
DA70 |
Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one.
••• |
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DQA1 |
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DA1 |
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DA10 |
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DA19 |
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DA28 |
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DA37 |
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DA46 |
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DA55 |
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DA64 |
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DA0 |
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DA9 |
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DA18 |
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DA27 |
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DA36 |
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DA45 |
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MA0 |
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MA1 |
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MA6 |
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Figure 5: Mapping Between COLM Packet and D Packet for WR Command
Page 11 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
ROW-to-ROW Packet Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T
CTM/CFM
tRRDELAY
ROW2 |
ROPa a0 |
ROPb b0 |
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Transaction a: ROPa |
a0 = {Da,Ba,Ra} |
Transaction b: ROPb |
b0= {Db,Bb,Rb} |
Figure 6: ROW-to-ROW Packet InteractionTiming
Figure 6 shows two packets on the ROW pins separated by
an interval tRRDELAY which depends upon the packet contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table 10 summarizes the tRRDELAY values for all possible cases.
Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, tRRDELAY is tRC (tRAS to the PRER command, and tRP to the next ACT).
Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the tRAS restriction means the activated bank must wait before it can be precharged.
Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba±1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait tRP for the sense amp and bank to precharge before being activated.
Table 10: ROW-to-ROW Packet Interaction - Rules
Case # |
ROPa |
Da |
Ba |
Ra |
|
ROPb |
Db |
Bb |
Rb |
tRRDELAY |
Example |
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|
RR1 |
ACT |
Da |
Ba |
Ra |
|
ACT |
/= Da |
xxxx |
x..x |
tPACKET |
Figure 11 |
RR2 |
ACT |
Da |
Ba |
Ra |
|
ACT |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
tRR |
Figure 11 |
RR3 |
ACT |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba+1,Ba-1} |
x..x |
tRC - illegal unless PRER to Ba/Ba+1/Ba-1 |
Figure 10 |
RR4 |
ACT |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba} |
x..x |
tRC - illegal unless PRER to Ba/Ba+1/Ba-1 |
Figure 10 |
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RR5 |
ACT |
Da |
Ba |
Ra |
|
PRER |
/= Da |
xxxx |
x..x |
tPACKET |
Figure 11 |
RR6 |
ACT |
Da |
Ba |
Ra |
|
PRER |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
tPACKET |
Figure 11 |
RR7 |
ACT |
Da |
Ba |
Ra |
|
PRER |
== Da |
== { Ba+1,Ba-1} |
x..x |
tRAS |
Figure 10 |
RR8 |
ACT |
Da |
Ba |
Ra |
|
PRER |
== Da |
== {Ba} |
x..x |
tRAS |
Figure 15 |
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RR9 |
PRER |
Da |
Ba |
Ra |
|
ACT |
/= Da |
xxxx |
x..x |
tPACKET |
Figure 12 |
RR10 |
PRER |
Da |
Ba |
Ra |
|
ACT |
== Da |
/= {Ba,Ba±1,Ba±2} |
x..x |
tPACKET |
Figure 12 |
RR10a |
PRER |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba+2} |
x..x |
tPACKET/tRP if Ba+1 is precharged/activated. |
|
RR10b |
PRER |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba-2} |
x..x |
tPACKET/tRP if Ba-1 is precharged/activated. |
|
RR11 |
PRER |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba+1,Ba-1} |
x..x |
tRP |
Figure 10 |
RR12 |
PRER |
Da |
Ba |
Ra |
|
ACT |
== Da |
== {Ba} |
x..x |
tRP |
Figure 10 |
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RR13 |
PRER |
Da |
Ba |
Ra |
|
PRER |
/= Da |
xxxx |
x..x |
tPACKET |
Figure 12 |
RR14 |
PRER |
Da |
Ba |
Ra |
|
PRER |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
tPP |
Figure 12 |
RR15 |
PRER |
Da |
Ba |
Ra |
|
PRER |
== Da |
== {Ba+1,Ba-1} |
x..x |
tPP |
Figure 12 |
RR16 |
PRER |
Da |
Ba |
Ra |
|
PRER |
== Da |
== Ba |
x..x |
tPP |
Figure 12 |
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Page 12 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
ROW-to-ROW Interaction - continued
Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, tPP applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the tPP restriction.
Two adjacent banks can’t be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later sections (see Table 7 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval tRCDELAY which depends upon the packet contents. Table 11 summarizes the
tRCDELAY values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T
CTM/CFM
ROW2 |
ROPa a0 |
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tRCDELAY |
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..ROW0 |
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COL4 |
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COPb b1 |
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..COL0 |
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DQA8..0 |
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DQB8..0 |
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Transaction a: ROPa |
a0 = {Da,Ba,Ra} |
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Transaction b: COPb |
b1= {Db,Bb,Cb1} |
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Figure 7: ROW-to-COL Packet InteractionTiming
Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in
Figure 14.
Table 11: ROW-to-COL Packet Interaction - Rules
Case # |
ROPa |
Da |
Ba |
Ra |
|
COPb |
Db |
Bb |
Cb1 |
tRCDELAY |
Example |
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|
RC1 |
ACT |
Da |
Ba |
Ra |
|
NOCOP,RD,retire |
/= Da |
xxxx |
x..x |
0 |
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RC2 |
ACT |
Da |
Ba |
Ra |
|
NOCOP |
== Da |
xxxx |
x..x |
0 |
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RC3 |
ACT |
Da |
Ba |
Ra |
|
RD,retire |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
0 |
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RC4 |
ACT |
Da |
Ba |
Ra |
|
RD,retire |
== Da |
== {Ba+1,Ba-1} |
x..x |
Illegal |
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RC5 |
ACT |
Da |
Ba |
Ra |
|
RD,retire |
== Da |
== Ba |
x..x |
tRCD |
Figure 15 |
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RC6 |
PRER |
Da |
Ba |
Ra |
|
NOCOP,RD,retire |
/= Da |
xxxx |
x..x |
0 |
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RC7 |
PRER |
Da |
Ba |
Ra |
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NOCOP |
== Da |
xxxx |
x..x |
0 |
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RC8 |
PRER |
Da |
Ba |
Ra |
|
RD,retire |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
0 |
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RC9 |
PRER |
Da |
Ba |
Ra |
|
RD,retire |
== Da |
== {Ba+1,Ba-1} |
x..x |
Illegal |
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Page 13 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
COL-to-COL Packet Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T
CTM/CFM
ROW2
..ROW0
COL4 |
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tCCDELAY |
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COPa a1 COPb b1 |
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COPc c1 |
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..COL0 |
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DQA8..0 |
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DQB8..0 |
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Transaction a: COPa |
a1 = {Da,Ba,Ca1} |
|||||
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Transaction b: COPb |
b1 = {Db,Bb,Cb1} |
|||||
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Transaction c: COPc |
c1 = {Dc,Bc,Cc1} |
Figure 8: COL-to-COL Packet InteractionTiming
Figure 8 shows three arbitrary packets on the COL pins. Packets “b” and “c” must be separated by an interval
tCCDELAY which depends upon the command and address values in all three packets. Table 12 summarizes the
tCCDELAY values for all possible cases.
Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is
followed by a WR command, a gap of tCAC -tCWD must be inserted between the two COL packets. See Figure 4 for
more explanation of why this gap is needed. For cases CC1,
CC2, CC4, and CC5, there is no restriction (tCCDELAY is tCC).
In cases CC6 through CC10, COPb is a WR command and
COPc is a RD command. The tCCDELAY value needed between these two packets depends upon the command and
address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure 18 (right) provides a more detailed explanation of this case.
In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place.
Cases CC7, CC8, and CC9 have no restriction (tCCDELAY is tCC).
For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14.
Table 12: COL-to-COL Packet Interaction - Rules
Case # |
COPa |
Da |
Ba |
Ca1 |
COPb |
Db |
Bb |
Cb1 |
|
COPc |
Dc |
Bc |
Cc1 |
tCCDELAY |
Example |
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CC1 |
xxxx |
xxxxx |
x..x |
x..x |
NOCOP |
Db |
Bb |
Cb1 |
|
xxxx |
xxxxx |
x..x |
x..x |
tCC |
|
CC2 |
xxxx |
xxxxx |
x..x |
x..x |
RD,WR |
Db |
Bb |
Cb1 |
|
NOCOP |
xxxxx |
x..x |
x..x |
tCC |
|
CC3 |
xxxx |
xxxxx |
x..x |
x..x |
RD |
Db |
Bb |
Cb1 |
|
WR |
xxxxx |
x..x |
x..x |
tCC+tCAC -tCWD |
Figure 4 |
CC4 |
xxxx |
xxxxx |
x..x |
x..x |
RD |
Db |
Bb |
Cb1 |
|
RD |
xxxxx |
x..x |
x..x |
tCC |
Figure 15 |
CC5 |
xxxx |
xxxxx |
x..x |
x..x |
WR |
Db |
Bb |
Cb1 |
|
WR |
xxxxx |
x..x |
x..x |
tCC |
Figure 16 |
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CC6 |
WR |
== Db |
x |
x..x |
WR |
Db |
Bb |
Cb1 |
|
RD |
== Db |
x..x |
x..x |
tRTR |
Figure 18 |
CC7 |
WR |
== Db |
x |
x..x |
WR |
Db |
Bb |
Cb1 |
|
RD |
/= Db |
x..x |
x..x |
tCC |
|
CC8 |
WR |
/= Db |
x |
x..x |
WR |
Db |
Bb |
Cb1 |
|
RD |
== Db |
x..x |
x..x |
tCC |
|
CC9 |
NOCOP |
== Db |
x |
x..x |
WR |
Db |
Bb |
Cb1 |
|
RD |
== Db |
x..x |
x..x |
tCC |
|
CC10 |
RD |
== Db |
x |
x..x |
WR |
Db |
Bb |
Cb1 |
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RD |
== Db |
x..x |
x..x |
tCC |
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Page 14 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
COL-to-ROW Packet Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T
CTM/CFM
ROW2 |
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tCRDELAY |
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ROPb b0 |
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..ROW0 |
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COL4 |
COPa a1 |
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..COL0 |
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DQA8..0 |
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DQB8..0 |
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Transaction a: COPa |
a1= {Da,Ba,Ca1} |
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Transaction b: ROPb |
b0= {Db,Bb,Rb} |
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Figure 9: COL-to-ROW Packet InteractionTiming
Figure 9 shows arbitrary packets on the COL and ROW pins.
They must be separated by an interval tCRDELAY which depends upon the command and address values in the
packets. Table 13 summarizes the tCRDELAY value for all possible cases.
Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks.
Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged Case CR5 is illegal because an adjacent bank can’t be activated or precharged until bank Ba is precharged first.
In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The tRDP parameter specifies the required spacing.
Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The tRTP parameter specifies the required spacing.
Case CR8 is labeled “Hazardous” because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure 19 shows an example of what can happen when the retire is not able to happen before the precharge.
For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14.
A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are discussed in a later section.
Table 13: COL-to-ROW Packet Interaction - Rules
Case # |
COPa |
Da |
Ba |
Ca1 |
|
ROPb |
Db |
Bb |
Rb |
tCRDELAY |
Example |
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CR1 |
NOCOP |
Da |
Ba |
Ca1 |
|
x..x |
xxxxx |
xxxx |
x..x |
0 |
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CR2 |
RD/WR |
Da |
Ba |
Ca1 |
|
x..x |
/= Da |
xxxx |
x..x |
0 |
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CR3 |
RD/WR |
Da |
Ba |
Ca1 |
|
x..x |
== Da |
/= {Ba,Ba+1,Ba-1} |
x..x |
0 |
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CR4 |
RD/WR |
Da |
Ba |
Ca1 |
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ACT |
== Da |
== {Ba} |
x..x |
Illegal |
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CR5 |
RD/WR |
Da |
Ba |
Ca1 |
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ACT |
== Da |
== {Ba+1,Ba-1} |
x..x |
Illegal |
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CR6 |
RD |
Da |
Ba |
Ca1 |
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PRER |
== Da |
== {Ba,Ba+1,Ba-1} |
x..x |
tRDP |
Figure 15 |
CR7 |
retirea |
Da |
Ba |
Ca1 |
|
PRER |
== Da |
== {Ba,Ba+1,Ba-1} |
x..x |
tRTP |
Figure 16 |
CR8 |
WRb |
Da |
Ba |
Ca1 |
|
PRER |
== Da |
== {Ba,Ba+1,Ba-1} |
x..x |
0 |
Figure 19 |
CR9 |
xxxx |
Da |
Ba |
Ca1 |
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NOROP |
xxxxx |
xxxx |
x..x |
0 |
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a.This is any command which permits the write buffer of device Da to retire (see Table 8). “Ba” is the bank address in the write buffer.
b.This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.
Page 15 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
ROW-to-ROW Examples
Figure 10 shows examples of some of the ROW-to-ROW packet spacings from Table 10. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the tRAS and tRP timing parameters, the separation
between ACT commands to the same bank must also satisfy the tRC timing parameter (RR4).
When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules.
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a0 = {Da,Ba,Ra} |
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Same Device |
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Adjacent Bank |
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RR7 |
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a1 = {Da,Ba+1} |
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Same Device |
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Adjacent Bank |
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RR3 |
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b0 = {Da,Ba+1,Rb} |
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Same Device |
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Same Bank |
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RR4 |
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b0 = {Da,Ba,Rb} |
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Same Device |
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Adjacent Bank |
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RR11 |
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b0 = {Da,Ba+1,Rb} |
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Same Device |
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Same Bank |
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RR12 |
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b0 = {Da,Ba,Rb} |
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T0 T1 |
T2 T3 |
T4 T5 T6 T7 T8 T9 T10 |
T11 T12 |
T13 T14 |
T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T |
29 T |
30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47 |
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CTM/CFM |
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ROW2 |
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ACT a0 |
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PRER a1 |
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ACT b0 |
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..ROW0 |
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COL4 |
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..COL0 |
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tRAS |
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DQA8..0 |
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tRP |
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DQB8..0 |
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tRC |
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Figure 10: Row Packet Example |
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Figure 11 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table 10. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to
the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device.
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a0 = {Da,Ba,Ra} |
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Different Device |
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Any Bank |
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RR1 |
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b0 = {Db,Bb,Rb} |
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Same Device |
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Non-adjacent Bank |
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RR2 |
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c0 = {Da,Bc,Rc} |
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Different Device |
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Any Bank |
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RR5 |
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b0 = {Db,Bb,Rb} |
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Same Device |
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c0 = {Da,Bc,Rc} |
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T0 T1 |
T2 T3 T4 T5 |
T6 T7 |
T8 T9 T10 T11 T12T13 |
T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 |
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T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 |
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T46 T47 |
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CTM/CFM |
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ROW2 |
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ACT a0 |
ACT |
b0 |
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ACT a0 |
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ACT c0 |
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ACT a0 |
PRER |
b0 |
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ACT a0 |
PRER c0 |
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..ROW0 |
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tPACKET |
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tPACKET |
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tPACKET |
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tRR |
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COL4
..COL0
DQA8..0
DQB8..0
Figure 11: Row Packet Example
Page 16 |
Rev. 1.02 Jan. 2000 |
K4R271669A/K4R441869A |
Direct RDRAM™ |
Figure 12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 10. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be
spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the same device.
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a0 |
= {Da,Ba,Ra} |
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Different Device |
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Any Bank |
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RR13 |
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b0 = {Db,Bb,Rb} |
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Same Device |
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Non-adjacent Bank |
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RR14 |
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c0 |
= {Da,Bc,Rc} |
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Same Device |
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Adjacent Bank |
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RR15 |
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c0 |
= {Da,Ba,Rc} |
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Same Device |
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Same Bank |
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RR16 |
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c0 = {Da,Ba+1Rc} |
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Different Device |
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Any Bank |
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RR9 |
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b0 = {Db,Bb,Rb} |
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Same Device |
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RR10 |
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c0 |
= {Da,Bc,Rc} |
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T0 T1 |
T2 T3 T4 T5 |
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T6 T7 |
T8 T9 T10 T11 T12 |
T |
13 |
T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 |
T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 |
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T46 T47 |
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CTM/CFM |
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ROW2 |
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PRER a0 |
PRER |
b0 |
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PRER a0 |
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PRER c0 |
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PRER a0 |
ACT |
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PRER a0 |
ACT |
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..ROW0 |
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tPACKET |
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tPACKET |
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tPACKET |
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tPP |
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Figure 12: Row Packet Examples
Row and Column Cycle Description
Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing the value of a bit in a bank’s storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value.
Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank.
Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical.
Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation.
Intervals: The activate operation requires the interval
tRCD,MIN to complete. The hidden restore operation requires the interval tRAS,MIN - tRCD,MIN to complete. Column read
and write operations are also performed during the tRAS,MIN - tRCD,MIN interval (if more than about four column operations are performed, this interval must be increased). The
precharge operation requires the interval tRP,MIN to complete.
Adjacent Banks: An RDRAM with an “s” designation (256Kx32sx16/18) indicates it contains “split banks”. This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0, 15, 30, and 31are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations.
For example (referring to the block diagram of Figure 2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing.
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K4R271669A/K4R441869A |
Direct RDRAM™ |
Precharge Mechanisms
Figure 13 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time
tRAS after the ACT command, and a time tRP before the next ACT command. This timing will serve as a baseline against
which the other precharge mechanisms can be compared.
a0 = {Da,Ba,Ra}
a5 = {Da,Ba}
b0 = {Da,Ba,Rb}
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
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Figure 13: Precharge via PRER Command in ROWR Packet |
Figure 14 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is
offset a time tOFFP from the COLC packet with the RDA command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets.
Figure 14 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time tOFFP from the COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time tRTR after the COLC packet with
the WR command unless the second COLC contains a RD command to the same device. This is described in more detail in Figure 17.
Figure 14 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that
is offset a time tOFFP from the COLX packet with the PREX command.
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Rev. 1.02 Jan. 2000 |