Samsung K4S560832D-TC-L7C, K4S560832D-TC-L75, K4S560832D-TC-L1L, K4S560832D-TC-L1H Datasheet

K4S560832D CMOS SDRAM

Rev. 1.1 May. 2003

256Mbit SDRAM

8M x 8bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 1.1

May. 2003

* Samsung Electronics reserves the right to change products or specification without notice.

K4S560832D CMOS SDRAM

Rev. 1.1 May. 2003

Revision History

Revision 0.0 (Jan. , 2002)

- First release

Revision 0.1(May., 2003)

- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.

K4S560832D CMOS SDRAM

Rev. 1.1 May. 2003

The K4S560832D is 268,435,456 bits synchronous high data rate

Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabri-

cated with SAMSUNG's high performance CMOS technology. Syn-

chronous design allows precise cycle control with the use of

system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system appli-

cations.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

GENERAL DESCRIPTIONFEATURES

FUNCTIONAL BLOCK DIAGRAM

8M x 8Bit x 4 Banks Synchronous DRAM

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S560832D-TC/L7C 133MHz(CL=2)

LVTTL

54pin

TSOP(II)

K4S560832D-TC/L75 133MHz(CL=3)

K4S560832D-TC/L1H 100MHz(CL=2)

K4S560832D-TC/L1L 100MHz(CL=3)

Bank Select

Data Input Register

8M x 8

8M x 8

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row Decoder Col. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS

RAS CAS WE L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

8M x 8

8M x 8

Timing Register

* Samsung Electronics reserves the right to change products or specification without notice.

K4S560832D CMOS SDRAM

Rev. 1.1 May. 2003

VDD

DQ0

V

DDQ

N.C

DQ1

V

SSQ

N.C

DQ2

V

DDQ

N.C

DQ3

V

SSQ

N.C

V

DD

N.C

WE

CAS

RAS

CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

PIN CONFIGURATION (Top view)

VSS

DQ7

V

SSQ

N.C

DQ6

V

DDQ

N.C

DQ5

V

SSQ

N.C

DQ4

V

DDQ

N.C

V

SS

N.C/RFU

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

V

SS

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitcH)

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS

Chip select

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A

0 ~ A12 Address

Row/column addresses are multiplexed on the same pins.

Row address : RA

0 ~ RA12, Column address : CA0 ~ CA9

BA0 ~ BA1 Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS

low.

Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS

low.

Enables column access.

WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS

, WE active.

DQM Data input/output mask

Makes data output Hi-Z, t

SHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ

0 ~7 Data input/output Data inputs/outputs are multiplexed on the same pins.

V

DD

/V

SS

Power supply/ground Power and ground for the input buffers and the core logic.

V

DDQ/VSSQ Data output power/ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.