Samsung K4S160822DT-G-FH, K4S160822DT-G-F8, K4S160822DT-G-F7, K4S160822DT-G-F10, K4S160822DT-G-FL Datasheet

K4S160822D

CMOS SDRAM

2Mx8 SDRAM

1M x 8bit x 2 Banks Synchronous DRAM LVTTL

Revision 1.0

October 1999

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

Revision History

Revision 1.0 (October 1999)

- 2 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

1M x 8Bit x 2 Banks Synchronous DRAM

FEATURES

•JEDEC standard 3.3V power supply

•LVTTL compatible with multiplexed address

•Dual banks operation

•MRS cycle with address key programs

-. CAS latency ( 2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

•All inputs are sampled at the positive going edge of the system clock

•Burst read single-bit write operation

•DQM for masking

•Auto & self refresh

•15.6us refresh duty cycle(2K/32ms)

GENERAL DESCRIPTION

The K4S160822D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 1,048,576 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

Part No.	Max Freq.	Interface	Package
K4S160822DT-G/F7	143MHz
K4S160822DT-G/F8	125MHz		44
K4S160822DT-G/FH	100MHz	LVTTL	TSOP(II)
K4S160822DT-G/FL	100MHz
K4S160822DT-G/F10	100MHz

FUNCTIONAL BLOCK DIAGRAM

				I/O			LWE
Data Input Register				Control			LDQM

Bank Select

	Address		CounterRefresh	BufferRow	DecoderRow			1M x 8	AMPSense	BufferOutput
											DQi
CLK	Register		LRAS	LCBR	Buffer.Col			1M x 8
ADD
							Column Decoder
							Latency & Burst Length
	LCKE						Programming Register
		LRAS	LCBR		LWE	LCAS		LWCBR		LDQM
					Timing Register
	CLK	CKE		CS	RAS	CAS	WE	DQM
								* Samsung Electronics reserves the right to
									change products or specification without
									notice.
						- 3 -				Rev. 1.0 (Oct. 1999)

K4S160822D									CMOS SDRAM
PIN CONFIGURATION (Top view)
	VDD				1	44		VSS
	DQ0				2	43		DQ7
VSSQ					3	42		VSSQ
	DQ1				4	41		DQ6
VDDQ					5	40		VDDQ
	DQ2				6	39		DQ5
VSSQ					7	38		VSSQ
	DQ3				8	37		DQ4
VDDQ					9	36		VDDQ
	N.C				10	35		N.C/RFU
	N.C				11	34		N.C
		WE			12	33		DQM
	CAS				13	32		CLK
	RAS				14	31		CKE
		CS			15	30		N.C
		BA			16	29		A9
A10/AP					17	28		A8
		A0			18	27		A7
		A1			19	26		A6
		A2			20	25		A5	44Pin TSOP (II)
		A3			21	24		A4	(400mil x 725mil)
	VDD				22	23		VSS	(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

				Pin		Name	Input Function
		CLK				System clock	Active on the positive going edge to sample all inputs.
							Disables or enables device operation by masking or enabling all inputs except
		CS				Chip select
							CLK, CKE and DQM
							Masks system clock to freeze operation from the next clock cycle.
		CKE				Clock enable	CKE should be enabled at least one cycle prior to new command.
							Disable input buffers for power down in standby.
		A0 ~ A10/AP				Address	Row/column addresses are multiplexed on the same pins.
							Row address : RA0 ~ RA10, Column address : CA0 ~ CA8
		BA				Bank select address	Selects bank to be activated during row address latch time.
							Selects bank for read/write during column address latch time.
							Latches row addresses on the positive going edge of the CLK with RAS low.
		RAS				Row address strobe
							Enables row access & precharge.
							Latches column addresses on the positive going edge of the CLK with CAS low.
		CAS				Column address strobe
							Enables column access.
							Enables write operation and row precharge.
		WE				Write enable
							Latches data in starting from CAS, WE active.
		DQM				Data input/output mask	Makes data output Hi-Z, tSHZ after the clock and masks the output.
							Blocks data input when DQM active.
		DQ0 ~ 7				Data input/output	Data inputs/outputs are multiplexed on the same pins.
		VDD/VSS				Power supply/ground	Power and ground for the input buffers and the core logic.
		VDDQ/VSSQ				Data output power/ground	Isolated power supply and ground for the output buffers to provide improved noise
							immunity.
		N.C/RFU				No connection	This pin is recommended to be left No Connection on the device.
						/reserved for future use

- 4 -	Rev. 1.0 (Oct. 1999)

K4S160822D				CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol	Value		Unit
Voltage on any pin relative to VSS		VIN, VOUT	-1.0 ~ 4.6		V
Voltage on VDD supply relative to VSS		VDD, VDDQ	-1.0 ~ 4.6		V
Storage temperature		TSTG	-55 ~ +150		°C
Power dissipation		PD	1		W
Short circuit current		IOS	50		mA

Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter	Symbol	Min	Typ	Max	Unit	Note
Supply voltage	VDD, VDDQ	3.0	3.3	3.6	V
Input logic high voltage	VIH	2.0	3.0	VDDQ+0.3	V	1
Input logic low voltage	VIL	-0.3	0	0.8	V	2
Output logic high voltage	VOH	2.4	-	-	V	IOH = -2mA
Output logic low voltage	VOL	-	-	0.4	V	IOL = 2mA
Input leakage current (Inputs)	ILI	-10	-	10	uA	3
input leakage current (I/O pins)	ILO	-10	-	10	uA	3,4

Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2.VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3.Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Pin

Symbol

Min

Max

Unit

Clock

CCLK

2.5

4.0

pF

RAS, CAS, WE, CS, CKE, DQM

CIN

2.5

5.0

pF

Address

CADD

2.5

5.0

pF

DQ0 ~ DQ7

COUT

4.0

6.5

pF

- 5 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Parameter

Symbol

Test Condition

CAS

Version

Unit

Note

Latency

-7

-8

-H

-L

-10

Operating current

Burst length = 1

ICC1

tRC ³ tRC(min)

100

90

85

85

75

mA

1

(One bank active)

Io = 0 mA

Precharge standby current in

ICC2P

CKE £ VIL(max), tCC = 15ns

2

mA

power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

2

CKE ³ VIH(min),

³ VIH(min), tCC = 15ns

ICC2N

CS

15

Precharge standby current in

Input signals are changed one time during 30ns

mA

non power-down mode

ICC2NS

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

5

Input signals are stable

Active standby current in

ICC3P

CKE £ VIL(max), tCC = 15ns

3

mA

power-down mode

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

3

CKE ³ VIH(min),

³ VIH(min), tCC = 15ns

Active standby current in

ICC3N

CS

25

mA

Input signals are changed one time during 30ns

non power-down mode

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

(One bank active)

ICC3NS

15

mA

Input signals are stable

Io = 0 mA

3

120

110

95

95

95

Operating current

Page burst

ICC4

mA

1

(Burst mode)

2Banks activated

2

95

85

95

85

85

tCCD = 2CLKs

Refresh current

ICC5

tRC ³ tRC(min)

90

80

mA

2

Self refresh current

ICC6

CKE £ 0.2V

1

mA

3

250

uA

4

Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2.Measured with outputs open.

3.Refresh period is 32ms.

4.K4S160822DT-G**

5.K4S160822DT-F**

- 6 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200Ω

50Ω

Output

VOH (DC) = 2.4V, IOH = -2mA

Output

Z0 = 50Ω

50pF

VOL

(DC) = 0.4V, IOL = 2mA

50pF

870Ω

(Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

				Parameter			Symbol			Version			Unit	Note
								-7	-8	-H	-L	-10
	Row active to row active delay						tRRD(min)	14	16	20	20	20	ns	1
	RAS to CAS delay						tRCD(min)	20	20	20	20	26	ns	1
	Row precharge time						tRP(min)	20	20	20	20	26	ns	1
	Row active time						tRAS(min)	48	48	50	50	50	ns	1
							tRAS(max)			100			us
	Row cycle time						tRC(min)	68	68	70	70	80	ns	1
	Last data in to row precharge						tRDL(min)	7	8	10	10	12	ns	2
	Last data in to new col. address delay						tCDL(min)			1			CLK	2
	Last data in to burst stop						tBDL(min)			1			CLK	2
	Col. address to col. address delay						tCCD(min)			1			CLK	3
	Number of valid output data					CAS latency=3				2			ea	4
						CAS latency=2				1

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.

2.Minimum delay is required to complete write.

3.All parts allow every cycle column address change.

4.In case of row precharge interrupt, auto precharge and read burst stop.

- 7 -	Rev. 1.0 (Oct. 1999)

K4S160822D														CMOS SDRAM
	AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
	Parameter		Symbol	-7			-8				-H	-L		-10		Unit	Note
				Min		Max	Min		Max	Min	Max	Min	Max	Min	Max
	CLK cycle time	CAS latency=3	tCC	7		1000	8		1000	10	1000	10	1000	10	1000	ns	1
		CAS latency=2		10			12			10		12		13
	CLK to valid	CAS latency=3	tSAC			6			6		6		6		7	ns	1,2
	output delay	CAS latency=2				6			6		6		7		8
	Output data	CAS latency=3	tOH	3			3			3		3		3		ns	2
	hold time	CAS latency=2		3			3			3		3		3
	CLK high pulse width		tCH	3			3			3		3		3.5		ns	3
	CLK low pulse width		tCL	3			3			3		3		3.5		ns	3
	Input setup time		tSS	2			2			2		2		2.5		ns	3
	Input hold time		tSH	1			1			1		1		1		ns	3
	CLK to output in Low-Z		tSLZ	1			1			1		1		1		ns	2
	CLK to output	CAS latency=3	tSHZ			6			6		6		6		7	ns
	in Hi-Z	CAS latency=2				6			6		6		7		8

Notes : 1. Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

	Parameter	Symbol	Condition	Min	Typ	Max	Unit	Notes
	Output rise time	trh	Measure in linear	1.37		4.37	Volts/ns	4
			region : 1.2V ~1.8V
	Output fall time	tfh	Measure in linear	1.30		3.8	Volts/ns	4
			region : 1.2V ~1.8V
	Output rise time	trh	Measure in linear	2.8	3.9	5.6	Volts/ns	1,2,3
			region : 1.2V ~1.8V
	Output fall time	tfh	Measure in linear	2.0	2.9	5.0	Volts/ns	1,2,3
			region : 1.2V ~1.8V

Notes : 1. Output rise and fall time must be guaranteed across VDD and process range.

2.Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.

3.Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.

4.Measured into 50pF only, use these values to characterize to.

5.All measurements done with respect to VSS.

- 8 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

IBIS SPECIFICATION

IOH Characteristics (Pull-up)

	Voltage	100MHz	100MHz	66MHz
		Min	Max	Min
	(V)	I (mA)	I (mA)	I (mA)
	3.45		-2.4
	3.3		-27.3
	3.0	0.0	-74.1	-0.7
	2.6	-21.1	-129.2	-7.5
	2.4	-34.1	-153.3	-13.3
	2.0	-58.7	-197.0	-27.5
	1.8	-67.3	-226.2	-35.5
	1.65	-73.0	-248.0	-41.1
	1.5	-77.9	-269.7	-47.9
	1.4	-80.8	-284.3	-52.4
	1.0	-88.6	-344.5	-72.5
	0.0	-93.0	-502.4	-93.0

66MHz and 100MHz Pull-up

	0	0.5	1	1.5	2	2.5	3	3.5
	0
	-100
	-200
mA	-300
	-400
	-500
	-600
				Voltage

IOH Min (100MHz)

IOH Min (66MHz)

IOH Max (66 and 100MHz)

IOL Characteristics (Pull-down)

	Voltage	100MHz	100MHz	66MHz
		Min	Max	Min
	(V)	I (mA)	I (mA)	I (mA)
	0.0	0.0	0.0	0.0
	0.4	27.5	70.2	17.7
	0.65	41.8	107.5	26.9
	0.85	51.6	133.8	33.3
	1.0	58.0	151.2	37.6
	1.4	70.7	187.7	46.6
	1.5	72.9	194.4	48.0
	1.65	75.4	202.5	49.5
	1.8	77.0	208.6	50.7
	1.95	77.6	212.0	51.5
	3.0	80.3	219.6	54.2
	3.45	81.4	222.6	54.9

66MHz and 100MHz Pull-down

250
200
150
mA
100
50
0
0	0.5	1	1.5	2	2.5	3	3.5
			Voltage

IOL Min (100MHz)

IOL Min (66MHz)

IOL Max (100MHz)

- 9 -	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

VDD Clamp @ CLK, CKE, CS, DQM & DQ

VDD (V)	I (mA)
0.0	0.0
0.2	0.0
0.4	0.0
0.6	0.0
0.7	0.0
0.8	0.0
0.9	0.0
1.0	0.23
1.2	1.34
1.4	3.02
1.6	5.06
1.8	7.35
2.0	9.83
2.2	12.48
2.4	15.30
2.6	18.31

VSS Clamp @ CLK, CKE, CS, DQM & DQ

VSS (V)	I (mA)
-2.6	-57.23
-2.4	-45.77
-2.2	-38.26
-2.0	-31.22
-1.8	-24.58
-1.6	-18.37
-1.4	-12.56
-1.2	-7.57
-1.0	-3.37
-0.9	-1.75
-0.8	-0.58
-0.7	-0.05
-0.6	0.0
-0.4	0.0
-0.2	0.0
0.0	0.0

Minimum VDD clamp characteristic (Referenced to VDD)

	20
mA	15
	10
	5
	0

0

1

2

3

Voltage

I (mA)

Minimum VSS clamp current

-3

-2

-1

0

	0
	-10
mA	-20
	-30
	-40
	-50
	-60

Voltage

I (mA)

- 10	Rev. 1.0 (Oct. 1999)

K4S160822D									CMOS SDRAM
	FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
	K4S160822DT-7									(Unit : Number of clock)
	Frequency		CAS	tRC	tRAS	tRP	tRRD	tRCD	tCCD	tCDL	tRDL
			Latency	68ns	48ns	20ns	14ns	20ns	7ns	7ns	7ns
	143MHz (7.0ns)		3	10	7	3	2	3	1	1	1
	125MHz (8.0ns)		3	9	6	3	2	3	1	1	1
	100MHz (10.0ns)		2	7	5	2	2	2	1	1	1
	83MHz (12.0ns)		2	6	4	2	2	2	1	1	1
	75MHz (13.0ns)		2	6	4	2	2	2	1	1	1
	66MHz (15.0ns)		2	5	4	2	1	2	1	1	1
	K4S160822DT-8									(Unit : Number of clock)
	Frequency		CAS	tRC	tRAS	tRP	tRRD	tRCD	tCCD	tCDL	tRDL
			Latency	68ns	48ns	20ns	16ns	20ns	8ns	8ns	8ns
	125MHz (8.0ns)		3	9	6	3	2	3	1	1	1
	100MHz (10.0ns)		3	7	5	2	2	2	1	1	1
	83MHz (12.0ns)		2	6	4	2	2	2	1	1	1
	75MHz (13.0ns)		2	6	4	2	2	2	1	1	1
	66MHz (15.0ns)		2	5	4	2	2	2	1	1	1
	K4S160822DT-H									(Unit : Number of clock)
	Frequency		CAS	tRC	tRAS	tRP	tRRD	tRCD	tCCD	tCDL	tRDL
			Latency	70ns	50ns	20ns	20ns	20ns	10ns	10ns	10ns
	100MHz (10.0ns)		2	7	5	2	2	2	1	1	1
	83MHz (12.0ns)		2	6	5	2	2	2	1	1	1
	75MHz (13.0ns)		2	6	4	2	2	2	1	1	1
	66MHz (15.0ns)		2	5	4	2	2	2	1	1	1
	60MHz (16.7ns)		2	5	3	2	2	2	1	1	1
	K4S160822DT-L									(Unit : Number of clock)
	Frequency		CAS	tRC	tRAS	tRP	tRRD	tRCD	tCCD	tCDL	tRDL
			Latency	70ns	50ns	20ns	20ns	20ns	10ns	10ns	10ns
	100MHz (10.0ns)		3	7	5	2	2	2	1	1	1
	83MHz (12.0ns)		2	6	5	2	2	2	1	1	1
	75MHz (13.0ns)		2	6	4	2	2	2	1	1	1
	66MHz (15.0ns)		2	5	4	2	2	2	1	1	1
	60MHz (16.7ns)		2	5	3	2	2	2	1	1	1
	K4S160822DT-10									(Unit : Number of clock)
	Frequency		CAS	tRC	tRAS	tRP	tRRD	tRCD	tCCD	tCDL	tRDL
			Latency	80ns	50ns	26ns	20ns	26ns	10ns	10ns	12ns
	100MHz (10.0ns)		3	8	5	3	2	3	1	1	2
	83MHz (12.0ns)		3	7	5	3	2	3	1	1	1
	75MHz (13.0ns)		2	7	4	2	2	2	1	1	1
	66MHz (15.0ns)		2	6	4	2	2	2	1	1	1
	60MHz (16.7ns)		2	5	3	2	2	2	1	1	1

- 11	Rev. 1.0 (Oct. 1999)

K4S160822D

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

A10/AP

A9~ A0

Note

Register

Mode Register Set

H

X

L

L

L

L

X

OP CODE

1, 2

Auto Refresh

H

H

L

L

L

H

X

X

3

Refresh

Entry

L

3

Self

L

H

H

H

3

Refresh

Exit

L

H

X

X

H

X

X

X

3

Bank Active & Row Addr.

H

X

L

L

H

H

X

V

Row Address

Read &

Auto Precharge Disable

H

X

L

H

L

H

X

V

L

Column

4

Column Address

Address

Auto Precharge Enable

H

(A0~A8)

4, 5

Write &

Auto Precharge Disable

H

X

L

H

L

L

X

V

L

Column

4

Column Address

Address

Auto Precharge Enable

H

(A0~A8)

4, 5

Burst Stop

H

X

L

H

H

L

X

X

6

Precharge

Bank Selection

H

X

L

L

H

L

X

V

L

X

Both Banks

X

H

Entry

H

L

H

X

X

X

X

Clock Suspend or

X

L

V

V

V

Active Power Down

Exit

L

H

X

X

X

X

X

Entry

H

L

H

X

X

X

X

Precharge Power Down Mode

L

H

H

H

X

Exit

L

H

H

X

X

X

X

L

V

V

V

DQM

H

X

V

X

7

No Operation Command

H

X

H

X

X

X

X

X

L

H

H

H

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Note : 1. OP Code : Operand Code

A0 ~ A10/AP, BA : Program keys. (@MRS)

2.MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state.

4.BA : Bank select address.

If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected.

If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the assoiated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

- 12	Rev. 1.0 (Oct. 1999)

K4S160822D																										CMOS SDRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address		BA			A10/AP		A9			A8		A7			A6			A5		A4		A3				A2		A1		A0
Function		RFU			RFU		W.B.L				TM						CAS Latency					BT					Burst Length
		Test Mode								CAS Latency								Burst Type								Burst Length
A8		A7			Type			A6		A5		A4		Latency				A3		Type		A2		A1		A0		BT = 0		BT = 1
0		0		Mode Register Set				0		0	0			Reserved			0		Sequential		0			0		0	1		1
0		1			Reserved			0		0	1			-			1		Interleave		0			0		1	2		2
1		0			Reserved			0		1	0			2							0			1		0	4		4
1		1			Reserved			0		1	1			3							0			1		1	8		8
		Write Burst Length						1		0	0			Reserved							1			0		0	Reserved		Reserved
A9				Length				1		0	1			Reserved							1			0		1	Reserved		Reserved
0				Burst				1		1	0			Reserved							1			1		0	Reserved		Reserved
1				Single Bit				1		1	1			Reserved								1		1		1	Full Page		Reserved
																				Full Page Length : x4 (1024), x8 (512), x16 (256)

POWER UP SEQUENCE

1.Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle.

- 13	Rev. 1.0 (Oct. 1999)

K4S160822D																						CMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
	Initial Address									Sequential											Interleave
	A1			A0
	0			0	0				1			2			3			0		1				2			3
	0			1	1				2			3			0			1		0				3			2
	1			0	2				3			0			1			2		3				0			1
	1			1	3				0			1			2			3		2				1			0
BURST SEQUENCE (BURST LENGTH = 8)
	Initial Address									Sequential											Interleave
A2		A1		A0
0		0		0	0		1	2		3	4		5	6		7	0		1	2	3		4		5	6		7
0		0		1	1		2	3		4	5		6	7		0	1		0	3	2		5		4	7		6
0		1		0	2		3	4		5	6		7	0		1	2		3	0	1		6		7	4		5
0		1		1	3		4	5		6	7		0	1		2	3		2	1	0		7		6	5		4
1		0		0	4		5	6		7	0		1	2		3	4		5	6	7		0		1	2		3
1		0		1	5		6	7		0	1		2	3		4	5		4	7	6		1		0	3		2
1		1		0	6		7	0		1	2		3	4		5	6		7	4	5		2		3	0		1
1		1		1	7		0	1		2	3		4	5		6	7		6	5	4		3		2	1		0

- 14	Rev. 1.0 (Oct. 1999)