K4D263238M |
128M DDR SDRAM |
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
Revision 1.3
August 2001
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - |
Rev. 1.3 (Aug. 2001) |
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K4D263238M |
128M DDR SDRAM |
Revision History
Revision 1.3 (August 2, 2001)
•Removed K4D263238M-QC40 with VDD&VDDQ=2.8V
•Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V.
•Changed tCK(max) from 7ns to 10ns.
Revision 1.2 (July 12, 2001)
•Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4
•The specification for the 222MHz/250MHz is preliminary one.
Revision 1.1 (March 5, 2000)
•Added K4D263238M-QC40 with VDD&VDDQ=2.8V
•Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed. - Changed CAS latency of K4D263238M-QC45 from CL4 to CL3.
•Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK
- 2 - |
Rev. 1.3 (Aug. 2001) |
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K4D263238M |
128M DDR SDRAM |
Revision 1.0 (December 13, 2000)
•Defined capacitance values
•Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK
Revision 0.5 (December 8, 2000)
•Changed AC input level from Vref + 0.31V to Vref + 0.35V
•Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based.
•Changed VIN /VOUT/VDDQ in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V.
Revision 0.4 (November 29, 2000) - Preliminary
•Removed K4D263238M-QC40
•Several AC parameters of K4D263238M-QC45 have been changed
-Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns.
-Changed tDQSCK & tAC from 0.6ns to 0.7ns
-Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
-Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns
-Corrected tDAL from 5tCK to 6tCK
•Several AC parameters of K4D263238M-QC50 have been changed
-Changed tQH from tHP-0.6ns to tHP-0.45ns.
-Changed tDQSCK & tAC from 0.6ns to 0.7ns
-Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
-Corrected tDAL from 5tCK to 6tCK
•Several AC parameters of K4D263238M-QC55 have been changed
-Changed tDQSQ from 0.45ns to 0.5ns. Changed tOH from tHP-0.6ns to tHP-0.5ns.
-Changed tDQSCK & tAC from 0.6ns to 0.75ns
-Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns
-Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns.
-Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK
•Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
•Add DC Characteristics value
•Define VIH(max) / VIL(min) as a note in Power & DC operating Condition table
•Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.
•Changed IIL,IOL test condition from 0V< VIN <VDD+0.3V to 0V< VIN <VDD.
Revision 0.3 (June 8, 2000)
• Removed Block Write function
Revision 0.2 (April 10, 2000)
•Separated tRCD into tRCDRD and tRCDWR
-tRCDRD: Row to Column delay for READ
-tRCDWR: Row to Column delay at WRITE
Revision 0.1 (March 16, 2000)
•Define the spec based on Vdd&Vddq=2.5V
•Maximum target frequency upto 250MHz@CL4
•Removed Write Interrupt by Read function
Revision 0.0 (December 27, 1999) - Target Spec
• Defined Target Specification
- 3 - |
Rev. 1.3 (Aug. 2001) |
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K4D263238M |
128M DDR SDRAM |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
FEATURES
• |
2.5V ± 5% power supply |
• |
Data I/O transactions on both edges of Data strobe |
• |
SSTL_2 compatible inputs/outputs |
• |
DLL aligns DQ and DQS transitions with Clock transition |
• |
4 banks operation |
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Edge aligned data & data strobe output |
• MRS cycle with address key programs |
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Center aligned data & data strobe input |
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-. Read latency 3,4 (clock) |
• |
DM for write masking only |
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-. Burst length (2, 4, 8 and Full page) |
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Auto & Self refresh |
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-. Burst type (sequential & interleave) |
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32ms refresh period (4K cycle) |
• |
Full page burst length for sequential burst type only |
• |
100pin TQFP package |
• |
Start address of the full page burst should be even |
• |
Maximum clock frequency up to 222MHz |
• All inputs except data & DM are sampled at the positive |
• |
Maximum data rate up to 444Mbps/pin |
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going edge of the system clock |
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•Differential clock input
•No Write Interrupted by Read function
ORDERING INFORMATION
Part NO. |
Max Freq. |
Max Data Rate |
Interface |
Package |
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K4D263238M-QC45 |
222MHz |
444Mbps/pin |
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K4D263238M-QC50 |
200MHz |
400Mbps/pin |
SSTL_2 |
100 TQFP |
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K4D263238M-QC55 |
183MHz |
366Mbps/pin |
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K4D263238M-QC60 |
166MHz |
333Mbps/pin |
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GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
- 4 - |
Rev. 1.3 (Aug. 2001) |
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K4D263238M |
128M DDR SDRAM |
PIN CONFIGURATION (Top View)
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DQ28 |
VDDQ |
DQ27 |
DQ26 |
VSSQ |
DQ25 |
DQ24 |
VDDQ |
DQ15 |
DQ14 |
VSSQ |
DQ13 |
DQ12 |
VDDQ |
VSS |
VDD |
DQ11 |
DQ10 |
VSSQ |
DQ9 |
DQ8 |
VDDQ |
VREF |
DM3 |
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DM1 |
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CK |
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CK |
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CKE |
MCL |
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A8(AP) |
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80 |
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79 |
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78 |
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77 |
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76 |
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75 |
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74 |
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73 |
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72 |
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71 |
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70 |
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69 |
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68 |
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67 |
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66 |
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65 |
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64 |
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63 |
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62 |
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61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
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53 |
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52 |
51 |
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DQ29 |
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81 |
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50 |
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VSSQ |
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82 |
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49 |
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DQ30 |
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83 |
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48 |
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DQ31 |
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84 |
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47 |
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VSS |
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85 |
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46 |
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VDDQ |
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86 |
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45 |
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N.C |
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87 |
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44 |
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N.C |
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88 |
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100 Pin TQFP |
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43 |
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N.C |
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89 |
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42 |
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N.C |
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90 |
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41 |
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20 x 14 mm2 |
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N.C |
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91 |
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40 |
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VSSQ |
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92 |
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0.65mm pin Pitch |
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39 |
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RFU |
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93 |
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38 |
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|||||||||||||||||||||
DQS |
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94 |
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37 |
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|||||||
VDDQ |
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95 |
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36 |
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|||||||
VDD |
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96 |
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35 |
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|||||||
DQ0 |
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97 |
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34 |
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|||||||
DQ1 |
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98 |
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33 |
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|||||||
VSSQ |
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99 |
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32 |
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|||||||
DQ2 |
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100 |
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31 |
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|||||||
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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8 |
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9 |
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10 |
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11 |
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12 |
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13 |
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14 |
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15 |
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16 |
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17 |
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18 |
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19 |
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20 |
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21 |
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22 |
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23 |
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24 |
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25 |
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26 |
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27 |
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28 |
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29 |
30 |
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DQ3 |
VDDQ |
DQ4 |
DQ5 |
VSSQ |
DQ6 |
DQ7 |
VDDQ |
DQ16 |
DQ17 |
VSSQ |
DQ18 |
DQ19 |
VDDQ |
VDD |
VSS |
DQ20 |
DQ21 |
VSSQ |
DQ22 |
DQ23 |
VDDQ |
DM0 |
DM2 |
|
WE |
|
CAS |
|
RAS |
|
CS |
BA0 |
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BA1 |
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||||||||||||||||||||||||||||||
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A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A11
A10 VDD A3 A2 A1 A0
PIN DESCRIPTION
|
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|
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CK,CK |
Differential Clock Input |
|
BA0, BA1 |
Bank Select Address |
||||
|
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||
|
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CKE |
Clock Enable |
|
A0 ~A11 |
Address Input |
||||
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CS |
Chip Select |
|
DQ0 ~ DQ31 |
Data Input/Output |
||||
|
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RAS |
Row Address Strobe |
|
VDD |
Power |
||||
|
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CAS |
Column Address Strobe |
|
VSS |
Ground |
||||
|
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WE |
Write Enable |
|
VDDQ |
Power for DQ′s |
||||
|
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||
|
|
DQS |
Data Strobe |
|
VSSQ |
Ground for DQ′s |
||||
|
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||
|
|
DMi |
Data Mask |
|
MCL |
Must Connect Low |
||||
|
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|
|
RFU |
Reserved for Future Use |
|
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||||
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|
- 5 - |
Rev. 1.3 (Aug. 2001) |
|
|
|
|
K4D263238M |
|
|
|
|
|
|
|
|
|
128M DDR SDRAM |
||||||||
INPUT/OUTPUT FUNCTIONAL DESCRIPTION |
||||||||||||||||||
|
|
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Symbol |
|
Type |
|
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|
|
Function |
|||||||
|
|
|
|
|
|
|
|
|
|
The differential system clock Input. |
||||||||
CK, |
|
|
|
*1 |
|
Input |
|
All of the inputs are sampled on the rising edge of the clock except |
||||||||||
CK |
||||||||||||||||||
|
|
|
|
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|
|
|
|
|
DQ′s and DM′s that are sampled on both edges of the DQS. |
||||||||
|
|
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||||||
|
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|
|
Activates the CK signal when high and deactivates the CK signal |
||||||||
|
CKE |
|
Input |
|
when low. By deactivating the clock, CKE low indicates the Power |
|||||||||||||
|
|
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|
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|
|
down mode or Self refresh mode. |
||||||||
|
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|
|
CS enables the command decoder when low and disabled the com- |
||||||||
|
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||
|
|
CS |
|
Input |
|
mand decoder when high. When the command decoder is disabled, |
||||||||||||
|
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|
|
new commands are ignored but previous operations continue. |
||||||||
|
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||||||
|
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|
|
Latches row addresses on the positive going edge of the CK with |
||||||||
|
RAS |
|
Input |
|
||||||||||||||
|
|
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|
|
|||||||
|
RAS low. Enables row access & precharge. |
|||||||||||||||||
|
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|||||||||
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||||||
|
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|
|
Latches column addresses on the positive going edge of the CK with |
||||||||
|
CAS |
|
Input |
|
||||||||||||||
|
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|
|
|||||||
|
CAS low. Enables column access. |
|||||||||||||||||
|
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|||||||||
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||||||
|
|
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|
|
|
Enables write operation and row precharge. |
||||||||
|
|
WE |
|
Input |
|
|||||||||||||
|
|
|
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|
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|
|
||||||
|
|
Latches data in starting from CAS, WE active. |
||||||||||||||||
|
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|
|
|||||||||
|
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|
|
||||||||||||
DQS |
|
Input/Output |
|
Data input and output are synchronized with both edge of DQS. |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
Data In mask. Data In is masked by DM Latency=0 when DM is high |
||||||||
DM0 ~ DM3 |
|
Input |
|
in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. |
||||||||
|
|
|
|
|
|
|
||||||||||||
DQ0 ~ DQ31 |
|
Input/Output |
|
Data inputs/Outputs are multiplexed on the same pins. |
||||||||||||||
|
|
|
|
|
|
|
||||||||||||
BA0, BA1 |
|
Input |
|
Selects which bank is to be active. |
||||||||||||||
|
|
|
|
|
|
|
|
|
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|
|
||||||
|
|
|
|
|
|
|
|
|
|
Row/Column addresses are multiplexed on the same pins. |
||||||||
A0 ~ A11 |
|
Input |
|
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
Column address CA8 is used for auto precharge. |
||||||||
|
|
|
|
|
|
|
||||||||||||
VDD/VSS |
|
Power Supply |
|
Power and ground for the input buffers and core logic. |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
VDDQ/VSSQ |
|
Power Supply |
|
Isolated power supply and ground for the output buffers to provide |
||||||||||||||
|
|
improved noise immunity. |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
||||||||||||
VREF |
|
Power Supply |
|
Reference voltage for inputs, used for SSTL interface. |
||||||||||||||
|
|
|
|
|
|
|
||||||||||||
MCL |
|
Must Connect Low |
|
Must connect Low |
||||||||||||||
|
|
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|
|
*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin.
- 6 - |
Rev. 1.3 (Aug. 2001) |
|
|
|
|