Samsung K4E661612C-TL60, K4E641612C-TC60, K4E641612C-TC50, K4E641612C-TC45, K4E661612C-TL50 Datasheet

K4E661612C,K4E641612C

CMOS DRAM

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

•Part Identification

-K4E661612C-TC/L(3.3V, 8K Ref.)

-K4E641612C-TC/L(3.3V, 4K Ref.)

•Active Power Dissipation

		Unit : mW
Speed	8K	4K
-45	324	468
-50	288	432
-60	252	396

•Extended Data Out Mode operation

•2 CAS Byte/Word Read/Write operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Fast parallel test mode capability

•Self-refresh capability (L-ver only)

•LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic TSOP(II) packages

•+3.3V±0.3V power supply

• Refresh Cycles

FUNCTIONAL BLOCK DIAGRAM

Part

Refresh

Refresh time

NO.

cycle

Normal

L-ver

K4E661612C*

8K

64ms

128ms

RAS

Vcc

UCAS

Control

K4E641612C

4K

LCAS

Clocks

VBB Generator

Vss

W

* Access mode & RAS only refresh mode										Lower
	: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
								Row Decoder		Data in	DQ0
	CAS-before-RAS & Hidden refresh mode						Refresh Timer			Buffer
											to
	: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)						Refresh Control		I/O	Lower	DQ7
										Data out
									&
								Memory Array		Buffer
									Amps
											OE
•	Performance Range						Refresh Counter	4,194,304 x 16		Upper
								Cells		Data in
									Sense		DQ8
	Speed	tRAC	tCAC	tRC	tHPC	A0~A12	Row Address Buffer			Buffer
											to
	-45	45ns	12ns	74ns	17ns	(A0~A11)*1				Upper	DQ15
						A0~A8	Col. Address Buffer	Column Decoder		Data out
	-50	50ns	13ns	84ns	20ns					Buffer
						(A0~A9)*1
	-60	60ns	15ns	104ns	25ns		Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K4E661612C,K4E641612C

CMOS DRAM

PIN CONFIGURATION (Top Views)

• K4E661612C-T

• K4E641612C-T

VCC					1	50				VSS
DQ0					2	49				DQ15
DQ1					3	48				DQ14
DQ2					4	47				DQ13
DQ3					5	46				DQ12
VCC					6	45				VSS
DQ4					7	44				DQ11
DQ5					8	43				DQ10
DQ6					9	42				DQ9
DQ7					10	41				DQ8
N.C					11	40				N.C
VCC					12	39				VSS
W					13	38				LCAS
RAS					14	37				UCAS
N.C					15	36				OE
N.C					16	35				N.C
N.C					17	34				N.C
N.C					18	33				A12(N.C)*
A0					19	32				A11
A1					20	31				A10
A2					21	30				A9
A3					22	29				A8
A4					23	28				A7
A5					24	27				A6
VCC					25	26				VSS

									(400mil TSOP(II))
								*(N.C) : N.C for 4K Refresh Product
			Pin Name						Pin function
			A0 - A12						Address Inputs(8K Product)
			A0 - A11						Address Inputs(4K Product)
			DQ0 - 15						Data In/Out
			VSS						Ground
			RAS						Row Address Strobe
			UCAS						Upper Column Address Strobe
			LCAS						Lower Column Address Strobe
			W						Read/Write Input
			OE						Data Output Enable
			VCC						Power(+3.3V)
			N.C						No Connection

K4E661612C,K4E641612C					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Rating				Units
Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		V
Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		V
Storage Temperature	Tstg	-55	to	+150		°C
Power Dissipation	PD		1			W
Short Circuit Output Current	IOS Address		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol	Min	Typ	Max	Units
Supply Voltage		VCC	3.0	3.3	3.6	V
Ground		VSS	0	0	0	V
Input High Voltage		VIH	2.0	-	Vcc+0.3*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	V
*1	: Vcc+1.3V at pulse width≤15ns which is measured at VCC
*2	: -1.3 at pulse width≤15ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Parameter		Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,		II(L)	-5	5	uA
	all other pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V

K4E661612C,K4E641612C							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				K4E661612C		K4E641612C
		-45		90		130		mA
ICC1	Don′t care	-50		80		120		mA
		-60		70		110		mA
ICC2	Normal	Don′t care		1		1		mA
	L			1		1		mA
		-45		90		130		mA
ICC3	Don′t care	-50		80		120		mA
		-60		70		110		mA
		-45		100		100		mA
ICC4	Don′t care	-50		90		90		mA
		-60		80		80		mA
ICC5	Normal	Don′t care		0.5		0.5		mA
	L			200		200		uA
		-45		130		130		mA
ICC6	Don′t care	-50		120		120		mA
		-60		110		110		mA
ICC7	L	Don′t care		350		350		uA
ICCS	L	Don′t care		350		350		uA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)

ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V

W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.

K4E661612C,K4E641612C

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

-

5

pF

Input capacitance [RAS, UCAS, LCAS, W, OE]

CIN2

-

7

pF

Output capacitance [DQ0 - DQ15]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

							Parameter										Symbol		-45			-50			-60		Unit	Note
																		Min		Max	Min		Max	Min		Max	s
		Random read or write cycle time															tRC	74			84			104			ns
		Read-modify-write cycle time															tRWC	101			113			138			ns
																	tRAC
		Access time from RAS																		45			50			60	ns	3,4,10
																	tCAC
		Access time from CAS																		12			13			15	ns	3,4,5
		Access time from column address															tAA			23			25			30	ns	3,10
																	tCLZ
		CAS to output in Low-Z																3			3			3			ns	3
																	tCEZ
		Output buffer turn-off delay from CAS																3		13	3		13	3		13	ns	6,20
																	tOLZ
		OE to output in Low-Z																3			3			3			ns	3
		Transition time (rise and fall)															tT	1		50	1		50	1		50	ns	2
																	tRP
		RAS precharge time																25			30			40			ns
																	tRAS
		RAS pulse width																45		10K	50		10K	60		10K	ns
																	tRSH
		RAS hold time																8			8			10			ns
																	tCSH
		CAS hold time																35			38			40			ns
																	tCAS
		CAS pulse width																7		5K	8		10K	10		10K	ns
																	tRCD
		RAS to CAS delay time																11		33	11		37	14		45	ns	4
																	tRAD
		RAS to column address delay time																9		22	9		25	12		30	ns	10
																	tCRP
		CAS to RAS precharge time																5			5			5			ns
		Row address set-up time															tASR	0			0			0			ns
		Row address hold time															tRAH	7			7			10			ns
		Column address set-up time															tASC	0			0			0			ns	13
		Column address hold time															tCAH	7			7			10			ns	13
																	tRAL
		Column address to RAS lead time																23			25			30			ns
		Read command set-up time															tRCS	0			0			0			ns
																	tRCH
		Read command hold time referenced to CAS																0			0			0			ns	8
																	tRRH
		Read command hold time referenced to RAS																0			0			0			ns	8
		Write command hold time															tWCH	7			7			10			ns
		Write command pulse width															tWP	6			7			10			ns
																	tRWL
		Write command to RAS lead time																8			8			10			ns
																	tCWL
		Write command to CAS lead time																7			7			10			ns	16
		Data set-up time															tDS	0			0			0			ns	9,19

K4E661612C,K4E641612C																																								CMOS DRAM
	AC CHARACTERISTICS (Continued)
															Parameter																Symbol		-45			-50			-60		Units	Note
																																Min		Max	Min		Max	Min		Max
		Data hold time																													tDH	7			7			10			ns	9,19
		Refresh period (Normal)																													tREF			64			64			64	ms
		Refresh period (L-ver)																													tREF			128			128			128	ms
		Write command set-up time																													tWCS	0			0			0			ns	7
																															tCWD
		CAS to W delay time																														24			27			32			ns	7,15
																															tRWD
		RAS to W delay time																														57			64			77			ns	7
																															tAWD
		Column address to W delay time																														35			39			47			ns	7
																															tCSR
		CAS set-up time (CAS -before-RAS refresh)																														5			5			5			ns	17
																															tCHR
		CAS hold time (CAS -before-RAS refresh)																														10			10			10			ns	18
																															tRPC
		RAS to CAS precharge time																														5			5			5			ns
																															tCPA
		Access time from CAS precharge																																24			28			35	ns	3
		Hyper Page cycle time																													tHPC	17			20			25			ns	21
		Hyper Page read-modify-write cycle time																													tHPRWC	47			47			56			ns	21
																															tCP
		CAS precharge time (Hyper page cycle)																														6.5			7			10			ns	14
																															tRASP
		RAS pulse width (Hyper page cycle)																														45		200K	50		200K	60		200K	ns
																															tRHCP
		RAS hold time from CAS precharge																														24			30			35			ns
																															tOEA
		OE access time																																12			13			15	ns	3
																															tOED
		OE to data delay																														8			10			13			ns
																															tCPWD
		CAS precharge to W delay time																														36			41			52			ns
																															tOEZ
		Output buffer turn off delay time from OE																														3		11	3		13	3		13	ns	6
																															tOEH
		OE command hold time																														5			5			5			ns
		Write command set-up time (Test mode in)																													tWTS	10			10			10			ns	11
		Write command hold time (Test mode in)																													tWTH	10			10			10			ns	11
																															tWRP
		W to RAS precharge time (C-B-R refresh)																														10			10			10			ns
																															tWRH
		W to RAS hold time (C-B-R refresh)																														10			10			10			ns
		Output data hold time																													tDOH	4			5			5			ns
																															tREZ
		Output buffer turn off delay from RAS																														3		13	3		13	3		13	ns	6,20
																															tWEZ
		Output buffer turn off delay from W																														3		13	3		13	3		13	ns	6
																															tWED
		W to data delay																														8			15			15			ns
																															tOCH
		OE to CAS hold time																														5			5			5			ns
																															tCHO
		CAS hold time to OE																														5			5			5			ns
																															tOEP
		OE precharge time																														5			5			5			ns
																															tWPE
		W pulse width (Hyper Page Cycle)																														5			5			5			ns
																															tRASS
		RAS pulse width (C-B-R self refresh)																														100			100			100			us	22,23,24
																															tRPS
		RAS precharge time (C-B-R self refresh)																														74			90			110			ns	22,23,24
																															tCHS
		CAS hold time (C-B-R self refresh)																														-50			-50			-50			ns	22,23,24

K4E661612C,K4E641612C																					CMOS DRAM
TEST MODE CYCLE																							( Note 11 )
					Parameter							Symbol		-45			-50			-60		Units	Note
													Min		Max	Min		Max	Min		Max
	Random read or write cycle time											tRC	79			89			109			ns
	Read-modify-write cycle time											tRWC	110			121			145			ns
												tRAC
	Access time from RAS														50			55			65	ns	3,4,10,12
												tCAC
	Access time from CAS														17			18			20	ns	3,4,5,12
	Access time from column address											tAA			28			30			35	ns	3,10,12
												tRAS
	RAS pulse width												50		10K	55		10K	65		10K	ns
												tCAS
	CAS pulse width												12		10K	13		10K	15		10K	ns
												tRSH
	RAS hold time												18			18			20			ns
												tCSH
	CAS hold time												39			43			50			ns
												tRAL
	Column Address to RAS lead time												28			30			35			ns
												tCWD
	CAS to W delay time												29			35			39			ns	7
												tRWD
	RAS to W delay time												62			72			84			ns	7
												tAWD
	Column Address to W delay time												40			47			54			ns	7
	Hyper Page cycle time											tHPC	22			25			30			ns	21
	Hyper Page read-modify-write cycle time											tHPRWC	52			53			61			ns	21
												tRASP
	RAS pulse width (Hyper page cycle)												50		200K	55		200K	65		200K	ns
												tCPA
	Access time from CAS precharge														29			33			40	ns	3
												tOEA
	OE access time														17			18			20	ns	3
												tOED
	OE to data delay												13			18			20			ns
												tOEH
	OE command hold time												13			18			20			ns

K4E661612C,K4E641612C

CMOS DRAM

NOTES

1.An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved.

2.Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.

3.Measured with a load equivalent to 1 TTL load and 100pF.

4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.Assumes that tRCD³tRCD(max).

6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

7.tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS³tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD³tCWD(min), tRWD³tRWD(min) and tAWD³tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.

8.Either tRCH or tRRH must be satisfied for a read cycle.

9.This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles.

10.Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

11.These specifiecations are applied in the test mode.

12.In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

13.tASC, tCAH are referenced to the earlier CAS falling edge.

14.tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.

15.tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

K4E64(6)1612C Truth Table

	RAS	LCAS		UCAS	W	OE	DQ0 - DQ7	DQ8-DQ15	STATE
	H	X		X	X	X	Hi-Z	Hi-Z	Standby
	L	H		H	X	X	Hi-Z	Hi-Z	Refresh
	L	L		H	H	L	DQ-OUT	Hi-Z	Byte Read
	L	H		L	H	L	Hi-Z	DQ-OUT	Byte Read
	L	L		L	H	L	DQ-OUT	DQ-OUT	Word Read
	L	L		H	L	H	DQ-IN	-	Byte Write
	L	H		L	L	H	-	DQ-IN	Byte Write
	L	L		L	L	H	DQ-IN	DQ-IN	Word Write
	L	L		L	H	H	Hi-Z	Hi-Z	-

K4E661612C,K4E641612C

CMOS DRAM

16.tCWL is specified from W falling edge to the earlier CAS rising edge.

17.tCSR is referenced to earlier CAS falling before RAS transition low.

18.tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR tCHR

19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15							Din

20.If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

21.tASC³6ns, Assume tT=2.0ns, if tASC£6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".

22.If tRASS³100us, then RAS precharge time must use tRPS instead of tRP.

23.For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification.

24.For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.

K4E661612C,K4E641612C

CMOS DRAM

WORD READ CYCLE

				tRC
VIH -				tRAS	tRP
RAS
VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
UCAS
VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -
			tRAD	tRAL
	tASR	tRAH	tASC
				tCAH
VIH -	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W
VIL -
				tAA
VIH -				tOLZ
				tOEA
OE
VIL -
				tCAC	tCEZ
DQ0 ~ DQ7			tRAC	tCLZ	tOEZ
VOH -
		OPEN			DATA-OUT
VOL -
				tCAC	tCEZ
DQ8 ~ DQ15			tRAC	tCLZ	tOEZ
VOH -
		OPEN			DATA-OUT
VOL -

Don′t care

Undefined

K4E661612C,K4E641612C

CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC
				tRAS	tRP
VIH -
RAS
VIL -
	tCRP				tRPC
VIH -
UCAS
VIL -
	tCRP			tCSH
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -			tRAD
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W
VIL -					tCEZ
				tAA	tOEZ
VIH -				tOEA
OE
VIL -
				tCAC
DQ0 ~ DQ7			tRAC	tCLZ
VOH -		OPEN			DATA-OUT
VOL -

tOLZ

DQ8 ~ DQ15

VOH -

OPEN

VOL -

Don′t care

Undefined