Samsung K4F640412D-TC-L, K4F640412D-JC-L, K4F660412D-TC-L, K4F660412D-JC-L Datasheet

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K4F660412D,K4F640412D

CMOS DRAM

16M x 4bit CMOS Dynamic RAM with Fast Page Mode

DESCRIPTION

This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

•Part Identification

-K4F660412D-JC/L(3.3V, 8K Ref., SOJ)

-K4F640412D-JC/L(3.3V, 4K Ref., SOJ)

-K4F660412D-TC/L(3.3V, 8K Ref., TSOP)

-K4F640412D-TC/L(3.3V, 4K Ref., TSOP)

•Active Power Dissipation

		Unit : mW

Speed	8K	4K
-45	324	432
-50	288	396
-60	252	360

•Fast Page Mode operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•Fast parallel test mode capability

•LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic SOJ and TSOP(II) packages

•+3.3V±0.3V power supply

• Refresh Cycles

Part	Refresh	Refresh time
NO.	cycle	Normal	L-ver
K4F660412D*	8K	64ms	128ms
K4F640412D	4K	64ms	128ms
K4F640412D	4K

FUNCTIONAL BLOCK DIAGRAM

RAS	Control		Vcc
RAS	Control		Vcc
CAS	Clocks	VBB Generator	Vss

W
W

* Access mode & RAS only refresh mode
	: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)						Refresh Timer	Row Decoder
	CAS-before-RAS & Hidden refresh mode						Refresh Timer	Row Decoder
	CAS-before-RAS & Hidden refresh mode								I/O	Data in
	: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)									Data in
	: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)						Refresh Control			Buffer
							Refresh Control		&	Buffer
								Memory Array	&		DQ0
								Memory Array	Amps		DQ0
•	Performance Range						Refresh Counter	16,777,216 x 4			to
•	Performance Range							Cells			DQ3
								Cells	Sense		DQ3
	Speed	tRAC	tCAC	tRC	tPC	A0~A12	Row Address Buffer		Sense	Data out
	Speed	tRAC	tCAC	tRC	tPC	A0~A12	Row Address Buffer			Data out
	-45	45ns	12ns	80ns	31ns	(A0~A11)*1				Buffer	OE
	-45	45ns	12ns	80ns	31ns	A0~A10	Col. Address Buffer	Column Decoder
	-50	50ns	13ns	90ns	35ns	A0~A10	Col. Address Buffer	Column Decoder
	-50	50ns	13ns	90ns	35ns	(A0~A11)*1
	-60	60ns	15ns	110ns	40ns		Note) *1 : 4K Refresh
							Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K4F660412D,K4F640412D

CMOS DRAM

PIN CONFIGURATION (Top Views)

•K4F660412D-J

•K4F640412D-J

VCC		1	32	VSS
DQ0		2	31	DQ3

DQ1		3	30	DQ2

N.C		4	29	N.C

N.C		5	28	N.C

N.C		6	27	N.C


N.C		7	26	CAS


	W	8	25	OE


RAS		9	24	A12(N.C)*

A0		10	23	A11

A1		11	22	A10
A2		12	21	A9

A3		13	20	A8

A4		14	19	A7

A5		15	18	A6

VCC		16	17	VSS

(J : 400mil SOJ)

* (N.C) : N.C for 4K Refresh product

• K4F660412D-T

• K4F640412D-T

VCC		1	32	VSS
VCC		1	32	VSS
DQ0		2	31	DQ3
DQ0		2	31	DQ3
DQ1		3	30	DQ2
DQ1		3	30	DQ2
N.C		4	29	N.C


N.C		5	28	N.C
N.C		5	28	N.C
N.C		6	27	N.C
N.C		6	27	N.C
N.C		7	26	CAS
N.C		7	26	CAS
	W	8	25	OE
	W	8	25	OE
RAS		9	24	A12(N.C)*
RAS		9	24	A12(N.C)*
A0		10	23	A11
A0		10	23	A11
A1		11	22	A10
A1		11	22	A10
A2		12	21	A9


A3		13	20	A8
A3		13	20	A8
A4		14	19	A7
A4		14	19	A7
A5		15	18	A6


VCC		16	17	VSS

(T : 400mil TSOP(II))

			Pin Name				Pin Function

			A0 - A12				Address Inputs(8K Product)

			A0 - A11				Address Inputs(4K Product)

			DQ0 - 3				Data In/Out

			VSS				Ground


			RAS				Row Address Strobe


			CAS				Column Address Strobe


			W				Read/Write Input


			OE				Data Output Enable

			VCC				Power(+3.3V)

			N.C				No Connection

K4F660412D,K4F640412D					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS

Parameter	Symbol	Rating				Units

Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		V

Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		V

Storage Temperature	Tstg	-55	to	+150		°C

Power Dissipation	PD		1			W

Short Circuit Output Current	IOS Address		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol	Min	Typ	Max	Units

Supply Voltage		VCC	3.0	3.3	3.6	V

Ground		VSS	0	0	0	V

Input High Voltage		VIH	2.0	-	Vcc+0.3*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	V
*1	: Vcc+1.3V at pulse width≤15ns which is measured at VCC
*2	: -1.3 at pulse width≤15ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter	Symbol	Min	Max	Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,	II(L)	-5	5	uA
all other pins not under test=0 Volt)	II(L)	-5	5	uA
all other pins not under test=0 Volt)

Output Leakage Current	IO(L)	-5	5	uA
(Data out is disabled, 0V≤VOUT≤VCC)	IO(L)	-5	5	uA
(Data out is disabled, 0V≤VOUT≤VCC)

Output High Voltage Level(IOH=-2mA)	VOH	2.4	-	V

Output Low Voltage Level(IOL=2mA)	VOL	-	0.4	V

K4F660412D,K4F640412D						CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)

Symbol	Power	Speed		Max			Units

			K4F660412D		K4F640412D
			K4F660412D		K4F640412D

		-45	90		120		mA
ICC1	Don′t care	-50	80		110		mA
		-60	70		100		mA

ICC2	Normal	Don′t care	1		1		mA
ICC2	L	Don′t care	1		1		mA
	L		1		1		mA

		-45	90		120		mA
ICC3	Don′t care	-50	80		110		mA
		-60	70		100		mA

		-45	70		70		mA
ICC4	Don′t care	-50	60		60		mA
		-60	50		50		mA

ICC5	Normal	Don′t care	0.5		0.5		mA
ICC5	L	Don′t care	200		200		uA
	L		200		200		uA

		-45	120		120		mA
ICC6	Don′t care	-50	110		110		mA
		-60	100		100		mA

ICC7	L	Don′t care	350		350		uA

ICCS	L	Don′t care	350		350		uA

ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,

W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.

K4F660412D,K4F640412D

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

Input capacitance [RAS, CAS, W, OE]

CIN2

Output capacitance [DQ0 - DQ3]

CDQ

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

	Parameter	Symbol	-45			-50			-60		Units	Note

			Min	Max	Min		Max	Min		Max
			Min	Max	Min		Max	Min		Max

Random read or write cycle time		tRC	80		90			110			ns
Read-modify-write cycle time		tRWC	115		133			153			ns
		tRAC
Access time from RAS		tRAC		45			50			60	ns	3,4,10
		tCAC
Access time from CAS		tCAC		12			13			15	ns	3,4,5

Access time from column address		tAA		23			25			30	ns	3,10

		tCLZ
CAS to output in Low-Z		tCLZ	0		0			0			ns	3
Output buffer turn-off delay		tOFF	0	13	0		13	0		13	ns	6
Transition time (rise and fall)		tT	1	50	1		50	1		50	ns	2
		tRP
RAS precharge time		tRP	25		30			40			ns

		tRAS
RAS pulse width		tRAS	45	10K	50		10K	60		10K	ns

		tRSH
RAS hold time		tRSH	12		13			15			ns
		tCSH
CAS hold time		tCSH	45		50			60			ns
		tCAS
CAS pulse width		tCAS	12	10K	13		10K	15		10K	ns

		tRCD
RAS to CAS delay time		tRCD	18	33	20		37	20		45	ns	4

		tRAD
RAS to column address delay time		tRAD	13	22	15		25	15		30	ns	10

		tCRP
CAS to RAS precharge time		tCRP	5		5			5			ns

Row address set-up time		tASR	0		0			0			ns

Row address hold time		tRAH	8		10			10			ns

Column address set-up time		tASC	0		0			0			ns

Column address hold time		tCAH	8		10			10			ns

		tRAL
Column address to RAS lead time		tRAL	23		25			30			ns

Read command set-up time		tRCS	0		0			0			ns

		tRCH
Read command hold time referenced to CAS		tRCH	0		0			0			ns	8

		tRRH
Read command hold time referenced to RAS		tRRH	0		0			0			ns	8

Write command hold time		tWCH	8		10			10			ns
Write command pulse width		tWP	8		10			10			ns
		tRWL
Write command to RAS lead time		tRWL	13		15			15			ns

		tCWL
Write command to CAS lead time		tCWL	12		13			15			ns

Data set-up time		tDS	0		0			0			ns	9

Data hold time		tDH	10		10			10			ns	9

K4F660412D,K4F640412D															CMOS DRAM
	AC CHARACTERISTICS (Continued)

				Parameter		Symbol		-45			-50			-60		Units	Note
				Parameter		Symbol	Min		Max	Min		Max	Min		Max	Units	Note
							Min		Max	Min		Max	Min		Max
		Refresh period (Normal)				tREF			64			64			64	ms
		Refresh period (L-ver)				tREF			128			128			128	ms
		Write command set-up time				tWCS	0			0			0			ns	7
						tCWD
		CAS to W delay time				tCWD	32			36			38			ns	7
						tRWD
		RAS to W delay time				tRWD	67			73			83			ns	7
						tAWD
		Column address to W delay time				tAWD	43			48			53			ns	7
						tCPWD
		CAS precharge W delay time				tCPWD	48			53			60			ns
						tCSR
		CAS set-up time (CAS -before-RAS refresh)				tCSR	5			5			5			ns
						tCHR
		CAS hold time (CAS -before-RAS refresh)				tCHR	10			10			10			ns
						tRPC
		RAS to CAS precharge time				tRPC	5			5			5			ns
		Access time from			precharge	tCPA			26			30			35	ns	3
		Access time from	CAS		precharge	tCPA			26			30			35	ns	3
		Fast Page mode cycle time				tPC	31			35			40			ns
		Fast Page mode read-modify-write cycle time				tPRWC	70			76			85			ns
						tCP
		CAS precharge time (Fast page cycle)				tCP	9			10			10			ns
						tRASP
		RAS pulse width (Fast page cycle)				tRASP	45		200K	50		200K	60		200K	ns
						tRHCP
		RAS hold time from CAS precharge				tRHCP	28			30			35			ns
						tOEA
		OE access time				tOEA			12			13			15	ns	3
						tOED
		OE to data delay				tOED	12			13			13			ns
						tOEZ
		Output buffer turn off delay time from OE				tOEZ	0		13	0		13	0		13	ns	6
						tOEH
		OE command hold time				tOEH	12			13			15			ns
		Write command set-up time (Test mode in)				tWTS	10			10			10			ns	11
		Write command hold time (Test mode in)				tWTH	15			15			15			ns	11
						tWRP
		W to RAS precharge time (C-B-R refresh)				tWRP	10			10			10			ns
						tWRH
		W to RAS hold time (C-B-R refresh)				tWRH	10			10			10			ns
						tRASS
		RAS pulse width (C-B-R self refresh)				tRASS	100			100			100			us	13,14,15
						tRPS
		RAS precharge time (C-B-R self refresh)				tRPS	80			90			110			ns	13,14,15
						tCHS
		CAS hold time (C-B-R self refresh)				tCHS	-50			-50			-50			ns	13,14,15

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