Samsung K4E170412D-B, K4E160412D-F, K4E160412D-B, K4E160411D-F, K4E160411D-B Datasheet

K4E170411D, K4E160411D
K4E170412D, K4E160412D	CMOS DRAM

4M x 4Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and personal computer.

FEATURES

•Part Identification

-K4E170411D-B(F) (5V, 4K Ref.)

-K4E160411D-B(F) (5V, 2K Ref.)

-K4E170412D-B(F) (3.3V, 4K Ref.)

-K4E160412D-B(F) (3.3V, 2K Ref.)

•Active Power Dissipation

					Unit : mW
Speed		3.3V			5V
	4K		2K	4K		2K
-50	324		396	495		605
-60	288		360	440		550

• Extended Data Out Mode operation

(Fast Page Mode with Extended Data Out)

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•Fast parallel test mode capability

•TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic SOJ and TSOP(II) packages

•Single +5V±10% power supply (5V product)

•Single +3.3V±0.3V power supply (3.3V product)

•

Refresh Cycles

Part

VCC

Refresh

Refresh period

NO.

cycle

Normal

L-ver

K4E170411D

5V

4K

64ms

K4E170412D

3.3V

128ms

K4E160411D

5V

2K

32ms

K4E160412D

3.3V

•

Performance Range

Speed

tRAC

tCAC

tRC

tHPC

Remark

-50

50ns

15ns

84ns

20ns

5V/3.3V

-60

60ns

17ns

104ns

25ns

5V/3.3V

FUNCTIONAL BLOCK DIAGRAM

RAS

Control

Vcc

CAS

Clocks

VBB Generator

Vss

W

				Data in
	Refresh Timer	Row Decoder		Buffer
	Refresh Control		I/O
			&		DQ0
		Memory Array
			Amps
					to
	Refresh Counter	4,194,304 x4
					DQ3
		Cells	Sense
A0-A11	Row Address Buffer
(A0 - A10)*1				Data out
A0 - A9
	Col. Address Buffer	Column Decoder			OE
(A0 - A10)*1				Buffer
Note) *1 : 2K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K4E170411D, K4E160411D
K4E170412D, K4E160412D	CMOS DRAM

PIN CONFIGURATION (Top Views)

	• K4E17(6)0411(2)D-B												• K4E17(6)0411(2)D-F
	VCC					1	24		VSS		VCC							1	24		VSS
	DQ0					2	23		DQ3		DQ0							2	23		DQ3
	DQ1					3	22		DQ2		DQ1							3	22		DQ2
	W					4	21		CAS		W							4	21		CAS
	RAS					5	20		OE		RAS							5	20		OE
*A11(N.C)						6	19		A9	*A11(N.C)								6	19		A9
	A10					7	18		A8		A10							7	18		A8
	A0					8	17		A7		A0							8	17		A7
	A1					9	16		A6		A1							9	16		A6
	A2					10	15		A5		A2							10	15		A5
	A3					11	14		A4		A3							11	14		A4
	VCC					12	13		VSS		VCC							12	13		VSS

*A11 is N.C for K4E160411(2)D(5V/3.3V, 2K Ref. product)

B : 300mil 26(24) SOJ

F: 300mil 26(24) TSOP II

	Pin Name								Pin Function
	A0 - A11								Address Inputs (4K Product)
	A0 - A10								Address Inputs (2K Product)
	DQ0 - 3								Data In/Out
			VSS						Ground
									Row Address Strobe
			RAS
									Column Address Strobe
		CAS
									Read/Write Input
					W
									Data Output Enable
				OE
			VCC						Power(+5.0V)
									Power(+3.3V)
			N.C						No Connection (2K Ref. product)

K4E170411D, K4E160411D
K4E170412D, K4E160412D								CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol				Rating				Units
			3.3V				5V
Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		-1.0	to	+7.0	V
Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		-1.0	to	+7.0	V
Storage Temperature	Tstg	-55	to	+150		-55	to	+150	°C
Power Dissipation	PD		1				1		W
Short Circuit Output Current	IOS Address		50				50		mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol		3.3V			5V		Units
			Min	Typ	Max	Min	Typ	Max
Supply Voltage		VCC	3.0	3.3	3.6	4.5	5.0	5.5	V
Ground		VSS	0	0	0	0	0	0	V
Input High Voltage		VIH	2.0	-	VCC+0.3*1	2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	-1.0*2	-	0.8	V
*1	: VCC+1.3V/15ns(3.3V), VCC+2.0/20ns(5V), Pulse width is measured at VCC
*2	: -1.3V/15ns(3.3V), -2.0/20ns(5V), Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Max	Parameter	Symbol	Min	Max	Units
		Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,	II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	3.3V	Output Leakage Current	IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-2mA)	VOH	2.4	-	V
		Output Low Voltage Level(IOL=2mA)	VOL	-	0.4	V
		Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,	II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	5V	Output Leakage Current	IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-5mA)	VOH	2.4	-	V
		Output Low Voltage Level(IOL=4.2mA)	VOL	-	0.4	V

K4E170411D, K4E160411D
K4E170412D, K4E160412D								CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed				Max			Units
				K4E170412D	K4E160412D		K4E170411D	K4E160411D
ICC1	Don′t care	-50		90	110		90	110	mA
		-60		80	100		80	100	mA
ICC2	Normal	Don′t care		1	1		2	2	mA
	L			1	1		1	1	mA
ICC3	Don′t care	-50		90	110		90	110	mA
		-60		80	100		80	100	mA
ICC4	Don′t care	-50		80	90		80	90	mA
		-60		70	80		70	80	mA
ICC5	Normal	Don′t care		0.5	0.5		1	1	mA
	L			200	200		250	250	uA
ICC6	Don′t care	-50		90	110		90	110	mA
		-60		80	100		80	100	mA
ICC7	L	Don′t care		250	250		300	300	uA
ICCS	L	Don′t care		200	200		250	250	uA

ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)

ICC4* : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,

DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,

DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3, ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

K4E170411D, K4E160411D

K4E170412D, K4E160412D

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

CAS,

W,

OE]

Output capacitance [DQ0 - DQ3]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Random read or write cycle time

tRC

84

104

ns

Read-modify-write cycle time

tRWC

116

140

ns

Access time from

tRAC

50

60

ns

3,4,10

RAS

Access time from

tCAC

13

15

ns

3,4,5

CAS

Access time from column address

tAA

25

30

ns

3,10

to output in Low-Z

tCLZ

3

3

ns

3

CAS

Output buffer turn-off delay from

tCEZ

3

13

3

15

ns

6,14

CAS

to output in Low-Z

tOLZ

3

3

ns

3

OE

Transition time (rise and fall)

tT

2

50

2

50

ns

2

precharge time

tRP

30

40

ns

RAS

pulse width

tRAS

50

10K

60

10K

ns

RAS

hold time

tRSH

13

15

ns

RAS

hold time

tCSH

38

45

ns

CAS

pulse width

tCAS

8

10K

10

10K

ns

CAS

to

delay time

tRCD

20

37

20

45

ns

4

RAS

CAS

to column address delay time

tRAD

15

25

15

30

ns

10

RAS

to

precharge time

tCRP

5

5

ns

CAS

RAS

Row address set-up time

tASR

0

0

ns

Row address hold time

tRAH

10

10

ns

Column address set-up time

tASC

0

0

ns

Column address hold time

tCAH

8

10

ns

Column address to

lead time

tRAL

25

30

ns

RAS

Read command set-up time

tRCS

0

0

ns

Read command hold time referenced to

tRCH

0

0

ns

8

CAS

Read command hold time referenced to

tRRH

0

0

ns

8

RAS

Write command hold time

tWCH

10

10

ns

Write command pulse width

tWP

10

10

ns

Write command to

lead time

tRWL

13

15

ns

RAS

Write command to

lead time

tCWL

8

10

ns

CAS

K4E170411D, K4E160411D

K4E170412D, K4E160412D

CMOS DRAM

AC CHARACTERISTICS (Continued)

Parameter

Symbol

-50

-60

Units

Notes

Min

Max

Min

Max

Data set-up time

tDS

0

0

ns

9

Data hold time

tDH

8

10

ns

9

Refresh period (2K, Normal)

tREF

32

32

ms

Refresh period (4K, Normal)

tREF

64

64

ms

Refresh period (L-ver)

tREF

128

128

ms

Write command set-up time

tWCS

0

0

ns

7

to

delay time

tCWD

30

34

ns

7

CAS

W

to

delay time

tRWD

67

79

ns

7

RAS

W

Column address to

delay time

tAWD

42

49

ns

7

W

precharge to

delay time

tCPWD

47

54

ns

CAS

W

set-up time

-before-

refresh)

tCSR

5

5

ns

CAS

(CAS

RAS

hold time

-before-

refresh)

tCHR

10

10

ns

CAS

(CAS

RAS

to

precharge time

tRPC

5

5

ns

RAS

CAS

Access time from

precharge

tCPA

28

35

ns

3

CAS

Hyper Page cycle time

tHPC

20

25

ns

13

Hyper Page read-modify-write cycle time

tHPRWC

47

56

ns

13

precharge time (Hyper Page cycle)

tCP

8

10

ns

CAS

pulse width (Hyper Page cycle)

tRASP

50

200K

60

200K

ns

RAS

hold time from

precharge

tRHCP

30

35

ns

RAS

CAS

access time

tOEA

13

15

ns

OE

to data delay

tOED

13

15

ns

OE

Output buffer turn off delay time from

tOEZ

3

13

3

15

ns

6

OE

command hold time

tOEH

13

15

ns

OE

Write command set-up time (Test mode in)

tWTS

10

10

ns

11

Write command hold time (Test mode in)

tWTH

10

10

ns

11

to

precharge time(C

-B-

refresh)

tWRP

10

10

ns

W

RAS

R

to

hold time(C

-B-

refresh)

tWRH

10

10

ns

W

RAS

R

Output data hold time

tDOH

5

5

ns

Output buffer turn off delay from

tREZ

3

13

3

15

ns

6,14

RAS

Output buffer turn off delay from

tWEZ

3

13

3

15

ns

6

W

to data delay

tWED

15

15

ns

W

to

hold time

tOCH

5

5

ns

OE

CAS

hold time to

tCHO

5

5

ns

CAS

OE

precharge time

tOEP

5

5

ns

OE

pulse width (Hyper Page Cycle)

tWPE

5

5

ns

W

-B-

self refresh)

tRASS

100

100

us

15,16,17

RAS

pulse width (C

R

-B-

self refresh)

tRPS

90

110

ns

15,16,17

RAS

precharge time (C

R

tCHS

CAS

hold time (C

-B-R self refresh)

-50

-50

ns

15,16,17

K4E170411D, K4E160411D

K4E170412D, K4E160412D

CMOS DRAM

TEST MODE CYCLE

( Note 11 )

Parameter

Symbol

-50

-60

Units

Note

Min

Max

Min

Max

Random read or write cycle time

tRC

89

109

ns

Read-modify-write cycle time

tRWC

121

145

ns

Access time from

tRAC

55

65

ns

3,4,10,12

RAS

Access time from

tCAC

18

20

ns

3,4,5,12

CAS

Access time from column address

tAA

30

35

ns

3,10,12

pulse width

tRAS

55

10K

65

10K

ns

RAS

pulse width

tCAS

13

10K

15

10K

ns

CAS

hold time

tRSH

18

20

ns

RAS

hold time

tCSH

43

50

ns

CAS

Column address to

lead time

tRAL

30

35

ns

RAS

to

delay time

tCWD

35

39

ns

7

CAS

W

to

delay time

tRWD

72

84

ns

7

RAS

W

Column address to

delay time

tAWD

47

54

ns

7

W

precharge to

delay time

tCPWD

52

59

ns

CAS

W

Hyper Page cycle time

tHPC

25

30

ns

13

Hyper Page read-modify-write cycle time

tHPRWC

53

61

ns

13

pulse width (Hyper Page cycle)

tRASP

55

200K

65

200K

ns

RAS

Access time from

precharge

tCPA

33

40

ns

3

CAS

access time

tOEA

18

20

ns

OE

to data delay

tOED

18

20

ns

OE

command hold time

tOEH

18

20

ns

OE