Samsung K4E660812C-JC-6, K4E660812C-JC-5, K4E660812C-TCL-6, K4E660812C-TCL-5, K4E660812C-TCL-45 Datasheet

K4E660812C,K4E640812C

CMOS DRAM

8M x 8bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

•Part Identification

-K4E660812C-JC/L(3.3V, 8K Ref.)

-K4E640812C-JC/L(3.3V, 4K Ref.)

-K4E660812C-TC/L(3.3V, 8K Ref.)

-K4E640812C-TC/L(3.3V, 4K Ref.)

•Active Power Dissipation

		Unit : mW
Speed	8K	4K
-45	324	432
-50	288	396
-60	252	360

• Refresh Cycles

	Part	Refresh	Refresh time
	NO.	cycle	Normal	L-ver
	K4E660812C*	8K	64ms	128ms
	K4E640812C	4K

•Extended Data Out Mode operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•Fast parallel test mode capability

•LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in Plastic SOJ and TSOP(II) packages

•+3.3V±0.3V power supply

FUNCTIONAL BLOCK DIAGRAM

RAS

Control

Vcc

CAS

Clocks

VBB Generator

Vss

W

*	Access mode & RAS only refresh mode
	: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)						Refresh Timer	Row Decoder
	CAS-before-RAS & Hidden refresh mode								& I/O	Data in
	: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)						Refresh Control	Memory Array		Buffer	DQ0
									Amps
	Performance Range:						Refresh Counter	8,388,608 x 8			to
¡Ü								Cells	Sense		DQ7
	Speed	tRAC	tCAC	tRC	tHPC	A0~A12	Row Address Buffer			Data out	OE
	-45	45ns	12ns	74ns	17ns	(A0~A11)*1				Buffer
						A0~A9	Col. Address Buffer	Column Decoder
	-50	50ns	13ns	84ns	20ns	(A0~A10)*1
	-60	60ns	15ns	104ns	25ns		Note) *1 : 4K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K4E660812C,K4E640812C

CMOS DRAM

PIN CONFIGURATION (Top Views)

•K4E660812C-J

•K4E640812C-J

VCC				1	32		VSS
DQ0				2	31		DQ7
DQ1				3	30		DQ6
DQ2				4	29		DQ5
DQ3				5	28		DQ4
N.C				6	27		VSS
VCC				7	26		CAS
	W			8	25		OE
RAS				9	24		A12(N.C)*
A0				10	23		A11
A1				11	22		A10
A2				12	21		A9
A3				13	20		A8
A4				14	19		A7
A5				15	18		A6
VCC				16	17		VSS

(J : 400mil SOJ)

* (N.C) : N.C for 4K Refresh product

•K4E660812C-T

•K4E640812C-T

VCC					1	32		VSS
DQ0					2	31		DQ7
DQ1					3	30		DQ6
DQ2					4	29		DQ5
DQ3					5	28		DQ4
N.C					6	27		VSS
VCC					7	26
								CAS
	W				8	25		OE
RAS					9	24		A12(N.C)*
A0					10	23		A11
A1					11	22		A10
A2					12	21		A9
A3					13	20		A8
A4					14	19		A7
A5					15	18		A6
VCC					16	17		VSS

(T : 400mil TSOP(II))

			Pin Name				Pin Function
			A0 - A12				Address Inputs(8K Product)
			A0 - A11				Address Inputs(4K Product)
			DQ0 - 7				Data In/Out
			VSS				Ground
			RAS				Row Address Strobe
			CAS				Column Address Strobe
			W				Read/Write Input
			OE				Data Output Enable
			VCC				Power(+3.3V)
			N.C				No Connection

K4E660812C,K4E640812C					CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Rating				Units
Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		V
Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		V
Storage Temperature	Tstg	-55	to	+150		°C
Power Dissipation	PD		1			W
Short Circuit Output Current	IOS Address		50			mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol	Min	Typ	Max	Units
Supply Voltage		VCC	3.0	3.3	3.6	V
Ground		VSS	0	0	0	V
Input High Voltage		VIH	2.0	-	Vcc+0.3*1	V
Input Low Voltage		VIL	-0.3*2	-	0.8	V
*1	: Vcc+1.3V at pulse width≤15ns which is measured at VCC
*2	: -1.3 at pulse width≤15ns which is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Parameter		Symbol	Min	Max	Units
	Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,		II(L)	-5	5	uA
	all other pins not under test=0 Volt)
	Output Leakage Current		IO(L)	-5	5	uA
	(Data out is disabled, 0V≤VOUT≤VCC)
	Output High Voltage Level(IOH=-2mA)		VOH	2.4	-	V
	Output Low Voltage Level(IOL=2mA)		VOL	-	0.4	V

K4E660812C,K4E640812C							CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed			Max			Units
				K4E660812C		K4E640812C
		-45		90		120		mA
ICC1	Don′t care	-50		80		110		mA
		-60		70		100		mA
ICC2	Normal	Don′t care		1		1		mA
	L			1		1		mA
		-45		90		120		mA
ICC3	Don′t care	-50		80		110		mA
		-60		70		100		mA
		-45		100		100		mA
ICC4	Don′t care	-50		90		90		mA
		-60		80		80		mA
ICC5	Normal	Don′t care		0.5		0.5		mA
	L			200		200		uA
		-45		120		120		mA
ICC6	Don′t care	-50		110		110		mA
		-60		100		100		mA
ICC7	L	Don′t care		350		350		uA
ICCS	L	Don′t care		350		350		uA

ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=CAS=W=VIH)

ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)

ICC4* : Extended Data Out Mode Current (RAS=VIL, CAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us

ICCS : Self Refresh Current

RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC.

K4E660812C,K4E640812C

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A12]

CIN1

-

5

pF

Input capacitance [RAS, CAS, W, OE]

CIN2

-

7

pF

Output capacitance [DQ0 - DQ7]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

						Parameter											Symbol	-45				-50			-60		Units	Note
																		Min		Max	Min		Max	Min		Max
		Random read or write cycle time															tRC	74			84			104			ns
		Read-modify-write cycle time															tRWC	101			113			138			ns
																	tRAC
		Access time from RAS																		45			50			60	ns	3,4,10
																	tCAC
		Access time from CAS																		12			13			15	ns	3,4,5
		Access time from column address															tAA			23			25			30	ns	3,10
																	tCLZ
		CAS to output in Low-Z																3			3			3			ns	3
																	tCEZ
		Output buffer turn-off delay from CAS																3		13	3		13	3		13	ns	6,13
																	tOLZ
		OE to output in Low-Z																3			3			3			ns	3
		Transition time (rise and fall)															tT	1		50	1		50	1		50	ns	2
																	tRP
		RAS precharge time																25			30			40			ns
																	tRAS
		RAS pulse width																45		10K	50		10K	60		10K	ns
																	tRSH
		RAS hold time																8			8			10			ns
																	tCSH
		CAS hold time																35			38			40			ns
																	tCAS
		CAS pulse width																7		5K	8		10K	10		10K	ns	14
																	tRCD
		RAS to CAS delay time																11		33	11		37	14		45	ns	4
																	tRAD
		RAS to column address delay time																9		22	9		25	12		30	ns	10
																	tCRP
		CAS to RAS precharge time																5			5			5			ns
		Row address set-up time															tASR	0			0			0			ns
		Row address hold time															tRAH	7			7			10			ns
		Column address set-up time															tASC	0			0			0			ns
		Column address hold time															tCAH	7			7			10			ns
																	tRAL
		Column address to RAS lead time																23			25			30			ns
		Read command set-up time															tRCS	0			0			0			ns
																	tRCH
		Read command hold time referenced to CAS																0			0			0			ns	8
																	tRRH
		Read command hold time referenced to RAS																0			0			0			ns	8
		Write command hold time															tWCH	7			7			10			ns
		Write command pulse width															tWP	6			7			10			ns
																	tRWL
		Write command to RAS lead time																8			8			10			ns
																	tCWL
		Write command to CAS lead time																7			7			10			ns
		Data set-up time															tDS	0			0			0			ns	9

K4E660812C,K4E640812C																																								CMOS DRAM
	AC CHARACTERISTICS (Continued)
														Parameter																	Symbol	-45				-50			-60		Units	Note
																																Min		Max	Min		Max	Min		Max
		Data hold time																													tDH	7			7			10			ns	9
		Refresh period (Normal)																													tREF			64			64			64	ms
		Refresh period (L-ver)																													tREF			128			128			128	ms
		Write command set-up time																													tWCS	0			0			0			ns	7
																															tCWD
		CAS to W delay time																														24			27			32			ns	7
																															tRWD
		RAS to W delay time																														57			64			77			ns	7
																															tAWD
		Column address to W delay time																														35			39			47			ns	7
																															tCSR
		CAS set-up time (CAS -before-RAS refresh)																														5			5			5			ns
																															tCHR
		CAS hold time (CAS -before-RAS refresh)																														10			10			10			ns
																															tRPC
		RAS to CAS precharge time																														5			5			5			ns
																															tCPA
		Access time from CAS precharge																																24			28			35	ns	3
		Hyper Page cycle time																													tHPC	17			20			25			ns	14
		Hyper Page read-modify-write cycle time																													tHPRWC	47			47			56			ns	14
																															tCP
		CAS precharge time (Hyper page cycle)																														6.5			7			10			ns
																															tRASP
		RAS pulse width (Hyper page cycle)																														45		200K	50		200K	60		200K	ns
																															tRHCP
		RAS hold time from CAS precharge																														24			30			35			ns
																															tOEA
		OE access time																																12			13			15	ns	3
																															tOED
		OE to data delay																														8			10			13			ns
																															tCPWD
		CAS precharge to W delay time																														36			41			52			ns
																															tOEZ
		Output buffer turn off delay time from OE																														3		11	3		13	3		13	ns	6
																															tOEH
		OE command hold time																														5			5			5			ns
		Write command set-up time (Test mode in)																													tWTS	10			10			10			ns	11
		Write command hold time (Test mode in)																													tWTH	10			10			10			ns	11
																															tWRP
		W to RAS precharge time (C-B-R refresh)																														10			10			10			ns
																															tWRH
		W to RAS hold time (C-B-R refresh)																														10			10			10			ns
		Output data hold time																													tDOH	4			5			5			ns
																															tREZ
		Output buffer turn off delay from RAS																														3		13	3		13	3		13	ns	6,13
																															tWEZ
		Output buffer turn off delay from W																														3		13	3		13	3		13	ns	6
																															tWED
		W to data delay																														8			15			15			ns
																															tOCH
		OE to CAS hold time																														5			5			5			ns
																															tCHO
		CAS hold time to OE																														5			5			5			ns
																															tOEP
		OE precharge time																														5			5			5			ns
																															tWPE
		W pulse width (Hyper Page Cycle)																														5			5			5			ns
																															tRASS
		RAS pulse width (C-B-R self refresh)																														100			100			100			us	15,16,17
																															tRPS
		RAS precharge time (C-B-R self refresh)																														74			90			110			ns	15,16,17
																															tCHS
		CAS hold time (C-B-R self refresh)																														-50			-50			-50			ns	15,16,17

K4E660812C,K4E640812C																					CMOS DRAM
TEST MODE CYCLE																							( Note 11 )
					Parameter							Symbol	-45				-50			-60		Units	Note
													Min		Max	Min		Max	Min		Max
	Random read or write cycle time											tRC	79			89			109			ns
	Read-modify-write cycle time											tRWC	110			121			145			ns
												tRAC
	Access time from RAS														50			55			65	ns	3,4,10,12
												tCAC
	Access time from CAS														17			18			20	ns	3,4,5,12
	Access time from column address											tAA			28			30			35	ns	3,10,12
												tRAS
	RAS pulse width												50		10K	55		10K	65		10K	ns
												tCAS
	CAS pulse width												12		10K	13		10K	15		10K	ns
												tRSH
	RAS hold time												18			18			20			ns
												tCSH
	CAS hold time												39			43			50			ns
												tRAL
	Column Address to RAS lead time												28			30			35			ns
												tCWD
	CAS to W delay time												29			35			39			ns	7
												tRWD
	RAS to W delay time												62			72			84			ns	7
												tAWD
	Column Address to W delay time												40			47			54			ns	7
	Hyper Page cycle time											tHPC	22			25			30			ns	14
	Hyper Page read-modify-write cycle time											tHPRWC	52			53			61			ns	14
												tRASP
	RAS pulse width (Hyper page cycle)												50		200K	55		200K	65		200K	ns
												tCPA
	Access time from CAS precharge														29			33			40	ns	3
												tOEA
	OE access time														17			18			20	ns	3
												tOED
	OE to data delay												13			18			20			ns
												tOEH
	OE command hold time												13			18			20			ns