Order this document by SG3525A/D
Pulse Width
Modulator Control Circuits
The SG3525A, SG3527A pulse width modulator control circuits offer improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on±chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common±mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. These devices also feature built±in soft±start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft±start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft±start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft±start capacitor when VCC is below nominal. The output stages are totem±pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off±state while the SG3527A utilized OR logic which gives a high output when off.
•8.0 V to 35 V Operation
•5.1 V ± 1.0% Trimmed Reference
•100 Hz to 400 kHz Oscillator Range
•Separate Oscillator Sync Pin
•Adjustable Deadtime Control
•Input Undervoltage Lockout
•Latching PWM to Prevent Multiple Pulses
•Pulse±by±Pulse Shutdown
•Dual Source/Sink Outputs: ±400 mA Peak
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Representative Block Diagram |
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Vref |
16 |
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VC |
15 |
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To Internal |
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13 |
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VCC |
Reference |
Circuitry |
Under± |
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Output A |
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12 |
Regulator |
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Voltage |
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Ground |
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Lockout |
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NOR |
11 |
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4 |
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OSC Output |
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Sync |
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Q |
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6 |
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F/F |
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Oscillator |
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RT |
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Q |
NOR |
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5 |
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CT |
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Output B |
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7 |
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Discharge |
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R |
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SG3525A Output Stage |
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9 |
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+ |
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S |
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13 |
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Compensation |
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± PWM |
Latch |
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1 |
±Error |
± |
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VC |
INV. Input |
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2 |
50μA |
S |
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Output A |
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Noninv. Input |
+Amp |
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8 |
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VREF |
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OR |
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CSoft±Start |
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Output B |
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10 |
5.0k |
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Shutdown |
5.0k |
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OR |
14 |
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SG3527A |
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Output Stage |
SG3525A
SG3527A
PULSE WIDTH MODULATOR
CONTROL CIRCUITS
SEMICONDUCTOR
TECHNICAL DATA
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N SUFFIX |
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PLASTIC PACKAGE |
16 |
CASE 648 |
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1 |
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DW SUFFIX |
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PLASTIC PACKAGE |
16 |
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CASE 751B |
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(SO±16L) |
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1 |
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PIN CONNECTIONS
Inv. Input |
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Vref |
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1 |
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16 |
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Noninv. Input |
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VCC |
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2 |
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15 |
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Sync |
3 |
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14 |
Output B |
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OSC. Output |
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VC |
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4 |
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13 |
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CT |
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Ground |
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5 |
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12 |
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RT |
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Output A |
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6 |
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11 |
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Discharge |
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7 |
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10 |
Shutdown |
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Soft±Start |
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Compensation |
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8 |
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9 |
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(Top View) |
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ORDERING INFORMATION
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Operating |
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Device |
Temperature Range |
Package |
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SG3525AN |
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Plastic DIP |
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TA = 0° to +70°C |
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SG3525ADW |
SO±16L |
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SG3527AN |
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Plastic DIP |
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Motorola, Inc. 1996 |
Rev 2 |
SG3525A SG3527A
MAXIMUM RATINGS (Note 1)
Rating |
Symbol |
Value |
Unit |
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Supply Voltage |
VCC |
+40 |
Vdc |
Collector Supply Voltage |
VC |
+40 |
Vdc |
Logic Inputs |
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±0.3 to +5.5 |
V |
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Analog Inputs |
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±0.3 to VCC |
V |
Output Current, Source or Sink |
IO |
±500 |
mA |
Reference Output Current |
Iref |
50 |
mA |
Oscillator Charging Current |
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5.0 |
mA |
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Power Dissipation (Plastic & Ceramic Package) |
PD |
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mW |
TA = +25°C (Note 2) |
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1000 |
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TC = +25°C (Note 3) |
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2000 |
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Thermal Resistance Junction±to±Air |
RθJA |
100 |
°C/W |
Thermal Resistance Junction±to±Case |
RθJC |
60 |
°C/W |
Operating Junction Temperature |
TJ |
+150 |
°C |
Storage Temperature Range |
Tstg |
±55 to +125 |
°C |
Lead Temperature (Soldering, 10 seconds) |
TSolder |
+300 |
°C |
NOTES: 1. Values beyond which damage may occur. |
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2. Derate at 10 mW/°C for ambient temperatures above +50°C. |
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3. Derate at 16 mW/°C for case temperatures above +25°C. |
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RECOMMENDED OPERATING CONDITIONS
Characteristics |
Symbol |
Min |
Max |
Unit |
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Supply Voltage |
VCC |
8.0 |
35 |
Vdc |
Collector Supply Voltage |
VC |
4.5 |
35 |
Vdc |
Output Sink/Source Current |
IO |
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±100 |
mA |
(Steady State) |
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0 |
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(Peak) |
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0 |
±400 |
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Reference Load Current |
Iref |
0 |
20 |
mA |
Oscillator Frequency Range |
fosc |
0.1 |
400 |
kHz |
Oscillator Timing Resistor |
RT |
2.0 |
150 |
kΩ |
Oscillator Timing Capacitor |
CT |
0.001 |
0.2 |
μF |
Deadtime Resistor Range |
RD |
0 |
500 |
Ω |
Operating Ambient Temperature Range |
TA |
0 |
+70 |
°C |
APPLICATION INFORMATION
Shutdown Options (See Block diagram, front page)
Since both the compensation and soft±start terminals (Pins 9 and 8) have current source pull±ups, either can readily accept a pull±down signal which only has to sink a maximum of 100 μA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM
latch is immediately set providing the fastest turn±off signal to the outputs; and a 150 μA current sink begins to discharge the external soft±start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft±start capacitor, thus, allowing, for example, a convenient implementation of pulse±by±pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn±on upon release.
Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
2 |
MOTOROLA ANALOG IC DEVICE DATA |
SG3525A SG3527A
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics |
Symbol |
Min |
Typ |
Max |
Unit |
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REFERENCE SECTION |
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Reference Output Voltage (TJ = +25°C) |
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Vref |
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5.00 |
5.10 |
5.20 |
Vdc |
Line Regulation (+8.0 V ≤ VCC ≤ +35 V) |
Regline |
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10 |
20 |
mV |
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Load Regulation (0 mA ≤ IL ≤ 20 mA) |
Regload |
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20 |
50 |
mV |
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Temperature Stability |
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Vref/ |
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T |
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20 |
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Total Output Variation |
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Vref |
4.95 |
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5.25 |
Vdc |
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Includes Line and Load Regulation over Temperature |
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Short Circuit Current |
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ISC |
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80 |
100 |
mA |
(Vref = 0 V, TJ = +25°C) |
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Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) |
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Vn |
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40 |
200 |
μVrms |
Long Term Stability (TJ = +125°C) (Note 5) |
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S |
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20 |
50 |
mV/khr |
OSCILLATOR SECTION (Note 6, unless otherwise noted.) |
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Initial Accuracy (TJ = +25°C) |
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±2.0 |
±6.0 |
% |
Frequency Stability with Voltage |
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fosc |
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±1.0 |
±2.0 |
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(+8.0 V ≤ VCC ≤ +35 V) |
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D VCC |
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Frequency Stability with Temperature |
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fosc |
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±0.3 |
± |
% |
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D |
T |
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Minimum Frequency (RT = 150 kΩ, CT = 0.2 μF) |
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fmin |
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50 |
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Hz |
Maximum Frequency (RT = 2.0 kΩ, CT = 1.0 nF) |
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fmax |
400 |
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kHz |
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Current Mirror (IRT = 2.0 mA) |
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1.7 |
2.0 |
2.2 |
mA |
Clock Amplitude |
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3.0 |
3.5 |
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V |
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Clock Width (TJ = +25°C) |
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0.3 |
0.5 |
1.0 |
μs |
Sync Threshold |
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1.2 |
2.0 |
2.8 |
V |
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Sync Input Current (Sync Voltage = +3.5 V) |
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± |
1.0 |
2.5 |
mA |
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ERROR AMPLIFIER SECTION (VCM = +5.1 V) |
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Input Offset Voltage |
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VIO |
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2.0 |
10 |
mV |
Input Bias Current |
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IIB |
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1.0 |
10 |
μA |
Input Offset Current |
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IIO |
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± |
1.0 |
μA |
DC Open Loop Gain (RL ≥ 10 MΩ) |
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AVOL |
60 |
75 |
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dB |
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Low Level Output Voltage |
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VOL |
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0.2 |
0.5 |
V |
High Level Output Voltage |
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VOH |
3.8 |
5.6 |
± |
V |
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Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) |
CMRR |
60 |
75 |
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dB |
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Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) |
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PSRR |
50 |
60 |
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dB |
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PWM COMPARATOR SECTION |
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Minimum Duty Cycle |
DCmin |
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0 |
% |
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Maximum Duty Cycle |
DCmax |
45 |
49 |
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% |
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Input Threshold, Zero Duty Cycle (Note 6) |
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Vth |
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0.6 |
0.9 |
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V |
Input Threshold, Maximum Duty Cycle (Note 6) |
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Vth |
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3.3 |
3.6 |
V |
Input Bias Current |
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IIB |
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0.05 |
1.0 |
μA |
NOTES: 4. Tlow = 0° for SG3525A, 3527A Thigh = +70°C for SG3525A, 3527A
5.Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot.
6.Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 μF, RD = 0Ω).
MOTOROLA ANALOG IC DEVICE DATA |
3 |
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