Mitsubishi M5M5V216AWG-55HI, M5M5V216AWG-55H, M5M5V216AWG-70LW, M5M5V216AWG-70LI, M5M5V216AWG-70L Datasheet

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Mitsubishi M5M5V216AWG-55HI, M5M5V216AWG-55H, M5M5V216AWG-70LW, M5M5V216AWG-70LI, M5M5V216AWG-70L Datasheet

revision-01, ' 98.12.08

MITSUBISHI LSIs

M5M5V216AWG

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM

DESCRIPTION

The M5M5V216A is a family of low voltage 2-Mbit static RAMs organized as 131,072-words by 16-bit, fabricated by Mitsubishi's high-performance 0.25µm CMOS technology.

The M5M5V216A is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives.

M5M5V216AWG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48pin) and ball pitch of 0.75mm. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards.

From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below.

FEATURES

Single +2.7~+3.6V power supply

Small stand-by current: 0.3µA(3V,typ.)

No clocks, No refresh

Data retention supply voltage=2.0V to 3.6V All inputs and outputs are TTL compatible.

Easy memory expansion by S , BC1 and BC2

Common Data I/O

Three-state outputs: OR-tie capability

OE prevents data contention in the I/O bus

Process technology: 0.25µm CMOS Package: 48 pin 7.0mm x8.5mm CSP

PART NAME TABLE

Version,		Power	Access	Stand-by current Icc(PD), Vcc=3.0V						Active
										current
Operating	Part name		time	typical *			Ratings (max.)
		Supply								Icc1
temperature			max.	25 C	40 C	25 C	40 C	70 C	85 C
										(3.0V, typ.)
	M5M5V216AWG -55L	2.7 ~ 3.6V	55ns(@ 2.7V) / 50ns(@3.3V)	---	---	---	---	20µA	---
Standard	M5M5V216AWG -70L		70ns(@ 2.7V) / 65ns(@3.3V)

0 ~ +70 C	M5M5V216AWG -55H	2.7 ~ 3.6V	55ns(@ 2.7V) / 50ns(@3.3V)	0.3µA	1µA	1µA	3µA	8µA	---
	M5M5V216AWG -70H		70ns(@ 2.7V) / 65ns(@3.3V)
										45mA
	M5M5V216AWG -55LW		55ns(@ 2.7V) / 50ns(@3.3V)
		2.7 ~ 3.6V		---	---	---	---			(10MHz)
W-version	M5M5V216AWG -70LW		70ns(@ 2.7V) / 65ns(@3.3V)					20µA	50µA


-20 ~ +85 C	M5M5V216AWG -55HW	2.7 ~ 3.6V	55ns(@ 2.7V) / 50ns(@3.3V)	0.3µA	1µA	1µA	3µA	8µA	24µA	5mA
	M5M5V216AWG -70HW		70ns(@ 2.7V) / 65ns(@3.3V)
										(1MHz)


	M5M5V216AWG -55L I	2.7 ~ 3.6V	55ns(@ 2.7V) / 50ns(@3.3V)	---	---	---	---
I-version	M5M5V216AWG -70L I		70ns(@ 2.7V) / 65ns(@3.3V)					20µA	50µA


-40 ~ +85 C	M5M5V216AWG -55H I	2.7 ~ 3.6V	55ns(@ 2.7V) / 50ns(@3.3V)	0.3µA	1µA	1µA	3µA	8µA	24µA
	M5M5V216AWG -70H I		70ns(@ 2.7V) / 65ns(@3.3V)

* "typical" parameter is sampled, not 100% tested.

PIN CONFIGURATION

(TOP VIEW)

(BOTTOM VIEW)

Function

A0 ~ A16 Address input

BC1

DQ1 ~ DQ16 Data input / output

BC2

Chip select input

Write control input

GND

Vcc

GND

Output inable input

Vcc

GND

A16

GND

A16

GND

Vcc

BC1

Lower Byte (DQ1 ~ 8)

Upper Byte (DQ9 ~ 16)

A14

BC2

Vcc

Power supply

A10

A13

A10

GND

Ground supply

A11

A12

A15

A12

A11

Outline: 48FJA

NC: No Connection

MITSUBISHI ELECTRIC

revision-01, ' 98.12.08

MITSUBISHI LSIs

M5M5V216AWG

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM

FUNCTION

The M5M5V216AWG is organized as 131,072-words by 16-bit. These devices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful.

The operation mode are determined by a combination of the device control inputs BC1 , BC2 , S , W and OE. Each mode is summarized in the function table.

A write operation is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S. The address(A0~A16) must be set up before the write cycle and must be stable during the entire cycle.

A read operation is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S are in an active state(S=L).

When setting BC1 at the high level and other pins are in an active stage , upper-byte are in a selesctable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high level and other pins are in an active stage, lowerbyte are in a selectable mode and upper-byte are in a non-selectable mode.

BLOCK DIAGRAM

When setting BC1 and BC2 at a high level or S at a high level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S.

The power supply current is reduced as low as 0.3µA(25 C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.

FUNCTION TABLE

Mode

Icc

BC1

BC2

DQ1~8

DQ9~16

Non selection

High-Z

Standby

Non selection

High-Z

Standby

Write

Din

High-Z

Active

Read

Dout

High-Z

Active

High-Z

Active

Write

High-Z

Din

Active

Read

High-Z

Dout

Active

High-Z

Active

Write

Din

Active

Read

Dout

Active

High-Z

Active

A0		DQ
		1
A1
MEMORY ARRAY		DQ
		DQ
131072	WORDS	8
131072	WORDS
x 16	BITS
A15	-	DQ
	-	DQ
		9
A16
	CLOCK	DQ
	GENERATOR	DQ
	GENERATOR	16
		16
S
BC1
BC2		Vcc
W
		GND
OE

MITSUBISHI ELECTRIC

revision-01, ' 98.12.08

MITSUBISHI LSIs

M5M5V216AWG

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Conditions			Ratings	Units
Vcc	Supply voltage	With respect to GND		-0.5* ~ +4.6		V
VI	Input voltage	With respect to GND		-0.5* ~ Vcc + 0.5		V
VO	Output voltage	With respect to GND		0	~ Vcc
Pd	Power dissipation	Ta=25 C			700	mW
	Operating	Standard	(-L, -H)	0	~ +70
Ta	Operating	W-version	(-LW, -HW)	- 20 ~ +85		C
Ta	temperature	W-version	(-LW, -HW)	- 20 ~ +85		C
	temperature	I-version	(-LI, -HI)	- 40 ~ +85
		I-version	(-LI, -HI)	- 40 ~ +85
Tstg	Storage temperature			- 65	~ +150	C

* -3.0V in case of AC (Pulse width <= 30ns)

DC ELECTRICAL CHARACTERISTICS

( Vcc=2.7 ~ 3.6V, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Units

Min

Typ

Max

VIH

High-level input voltage

2.0

Vcc+0.3V

VIL

Low-level input voltage

-0.3 *

0.6

VOH1

High-level output voltage 1

IOH= -0.5mA

2.4

OH2

High-level output voltage 2

IOH= -0.05mA

Vcc-0.5V

VOL

Low-level output voltage

IOL=2mA

0.4

Input leakage current

VI =0 ~ Vcc

±1

µA

Output leakage current

±1

BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc

Active supply current

BC1

and

BC2

<0.2V ,

<0.2V

f= 10MHz

Icc1

other inputs =< 0.2V or

=> Vcc-0.2V

( AC,MOS level )

f= 1MHz

Output - open (duty 100%)

Active supply current

BC1 and BC2=VIL , S=VIL

f= 10MHz

Icc2

other pins =VIH or VIL

( AC,TTL level )

f= 1MHz

Output - open (duty 100%)

< 1 >

-LW, -LI

+70 ~ +85 C

S => Vcc - 0.2V,

-L, -LW, -LI

+70 C

other inputs = 0 ~ Vcc

-HW, -HI

+70 ~ +85 C

Icc3

Stand by supply current

< 2 >

-H, -HW, -HI

+40 ~ +70 C

µA

( AC,MOS level )

=> Vcc - 0.2V

+25 ~ +40 C

BC1

and

BC2

S =< 0.2V

-H

0 ~ +25 C

0.3

Other inputs=0~Vcc

-HW

- 20 ~ +25 C

0.3

-HI

- 40 ~ +25 C

0.3

Stand by supply current

Icc4

BC1

and BC2=VIH , S=VIL or S=VIH

0.5

( AC,TTL level )

Other inputs= 0 ~ Vcc

Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25 C

* -3.0V in case of AC (Pulse width <= 30ns)

CAPACITANCE				(Vcc=2.7 ~ 3.6V, unless otherwise noted)
	Symbol	Parameter	Conditions			Limits		Units
	Symbol	Parameter			Min	Typ	Max


	CI	Input capacitance	VI=GND, VI=25mVrms, f=1MHz				8	pF
	CO	Output capacitance	VO=GND,VO=25mVrms, f=1MHz				10	pF
	CO	Output capacitance	VO=GND,VO=25mVrms, f=1MHz				10

MITSUBISHI ELECTRIC

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