Mitsubishi M5M5V416BTP-85LW, M5M5V416BTP-85LI, M5M5V416BTP-85L, M5M5V416BTP-85HW, M5M5V416BTP-85HI Datasheet

revision-P04, ' 98.12.16

MITSUBISHI LSIs

M5M5V416BTP,RT	PRELIMINARY
	Notice: This is not a final specification.
	Some parametric limits are subject to change
	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION	FEATURES

The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs organized as 262,144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.25µm CMOS technology .

The M5M5V416B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es.

M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small outline package. M5M5V416BTP (normal lead bend ty pe package) , M5M5V416BRT (rev erse lead bend ty pe package) , both ty pes are v ery easy t o design a printed circuit board.

From the point of operating temperature, the f amily is div ided into three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are summarized in the part name table below.

Single +2.7~+3.6V power supply

Small stand-by current: 0.3µA(3V,ty p.)

No clocks, No ref resh

Data retention supply v oltage=2.0V to 3.6V All inputs and outputs are TTL compatible.

Easy memory expansion by S1, S2, BC1 and BC2

Common Data I/O

Three-state outputs: OR-tie capability

OE prev ents data contention in the I/O bus

Process technology : 0.25µm CMOS Package: 44 pin 400mil TSOP (II)

Version,		Power	Access time	Stand-by current Icc(PD), Vcc=3.0V							Activ e
											current
Operating	Part name			ty pical *		Ratings (max.)
		Supply	max.								Icc1
temperature				25°C	40°C	25°C	40°C	70°C		85°C
											(3.0V, ty p.)
	M5M5V416BTP , RT -70L		70ns
	M5M5V416BTP , RT -85L	2.7 ~ 3.6V	85ns	---	---	---	---	20µA		---
Standard	M5M5V416BTP , RT -10L		100ns
0 ~ +70°C	M5M5V416BTP , RT -70H		70ns
	M5M5V416BTP , RT -85H	2.7 ~ 3.6V	85ns	0.3µA	1µA	1µA	3µA	10µA		---
	M5M5V416BTP , RT -10H		100ns
	M5M5V416BTP , RT -70LW		70ns
	M5M5V416BTP , RT -85LW	2.7 ~ 3.6V	85ns	---	---	---	---	20µA		40µA
W-v ersion	M5M5V416BTP , RT -10LW		100ns								40mA
-20 ~ +85°C	M5M5V416BTP , RT -70HW		70ns								(10MHz)
	M5M5V416BTP , RT -85HW	2.7 ~ 3.6V	85ns	0.3µA	1µA	1µA	3µA	10µA		20µA
											5mA
	M5M5V416BTP , RT -10HW		100ns
											(1MHz)
	M5M5V416BTP , RT -70LI		70ns	---	---	---	---	20µA		40µA
	M5M5V416BTP , RT -85LI	2.7 ~ 3.6V	85ns
I-v ersion	M5M5V416BTP , RT -10LI		100ns
-40 ~ +85°C	M5M5V416BTP , RT -70HI		70ns
	M5M5V416BTP , RT -85HI	2.7 ~ 3.6V	85ns	0.3µA	1µA	1µA	3µA	10µA		20µA
	M5M5V416BTP , RT -10HI		100ns

PIN CONFIGURATION

* "ty pical" parameter is sampled, not 100% tested.

	A4				1	44				A5				A5				44	1				A4
	A3				2	43				A6				A6				43	2				A3
	A2				3	42				A7				A7				42	3				A2
	A1				4	41			OE					OE				41	4				A1
	A0				5	40												40	5				A0
										BC2			BC2
					6	39												39	6
	S1									BC1			BC1										S1
DQ1					7	38				DQ16			DQ16					38	7				DQ1
DQ2					8	37				DQ15			DQ15					37	8				DQ2
DQ3					9	36				DQ14			DQ14					36	9				DQ3
DQ4					10	35				DQ13			DQ13					35	10				DQ4
Vcc					11	34			GND				GND					34	11				Vcc
GND					12	33				Vcc			Vcc					33	12			GND
DQ5					13	32				DQ12			DQ12					32	13				DQ5
DQ6					14	31				DQ11			DQ11					31	14				DQ6
DQ7					15	30				DQ10			DQ10					30	15				DQ7
DQ8					16	29			DQ9				DQ9					29	16				DQ8
					17	28												28	17
WE											S2			S2									WE
A15					18	27				A8				A8				27	18				A15
A14					19	26				A9				A9				26	19				A14
A13					20	25				A10				A10				25	20				A13
A12					21	24				A11				A11				24	21				A12
A16					22	23				A17				A17				23	22				A16
					44P3W-H														44P3W-J

Pin

Function

A0 ~ A17 Address input

DQ1 ~ DQ16 Data input / output

				Chip select input 1
	S1
	S2			Chip select input 2
				Write control input
	W
				Output enable input
OE
BC1				Lower	By te	(DQ1 ~ 8)
BC2				Upper	By te	(DQ9 ~ 16)
Vcc				Power supply
GND				Ground supply

Outline: 44P3W-H/J

NC: No Connection

MITSUBISHI ELECTRIC

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revision-P04, ' 98.12.16

MITSUBISHI LSIs

M5M5V416BTP,RT	PRELIMINARY
	Notice: This is not a final specification.
	Some parametric limits are subject to change
	4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

FUNCTION

The M5M5V416BTP,RT are organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul.

The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table.

A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle.

A read operation is executed by setting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H).

When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode.

BLOCK DIAGRAM

When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2.

The power supply current is reduced as low as 0.3µA(25 °C,

ty pical), and the memory

data can be held at +2V power

supply ,

enabling

battery

back-up operation

during

power

f ailure or power-down operation in the non-selected mode.

FUNCTION TABLE

S2

Icc

S1

BC1

BC2

W

OE

Mode

DQ1~8

DQ9~16

H

L

X

X

X

X

Non selection

High-Z

High-Z

Standby

L

L

X

X

X

X

Non selection

High-Z

High-Z

Standby

H

H

X

X

X

X

Non selection

High-Z

High-Z

Standby

X

X

H

H

X

X

Non selection

High-Z

High-Z

Standby

L

H

L

H

L

X

Write

Din

High-Z

Activ e

L

H

L

H

H

L

Read

Dout

High-Z

Activ e

L

H

L

H

H

H

High-Z

High-Z

Activ e

L

H

H

L

L

X

Write

High-Z

Din

Activ e

L

H

H

L

H

L

Read

High-Z

Dout

Activ e

L

H

H

L

H

H

High-Z

High-Z

Activ e

L

H

L

L

L

X

Write

Din

Din

Activ e

L

H

L

L

H

L

Read

Dout

Dout

Activ e

L

H

L

L

H

H

High-Z

High-Z

Activ e

A0		DQ
		1
A1
MEMORY ARRAY		DQ
262144	WORDS	8
x 16	BITS
A16	-	DQ
		9
A17
S1	CLOCK	DQ
	GENERATOR
		16
S2
BC1
BC2		Vcc
W
		GND
OE

MITSUBISHI ELECTRIC

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revision-P04, ' 98.12.16

MITSUBISHI LSIs

M5M5V416BTP,RT								PRELIMINARY
									Notice: This is not a final specification.
									Some parametric limits are subject to change
					4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
	Symbol	Parameter		Conditions			Ratings		Units
	Vcc	Supply v oltage		With respect to GND		-0.5* ~ +4.6			V
	VI	Input v oltage		With respect to GND		-0.5* ~ Vcc + 0.5
	VO	Output v oltage		With respect to GND		0 ~ Vcc
	Pd	Power dissipation		Ta=25°C			700		mW
		Operating		Standard	(-L, -H)	0	~ +70
	T a			W-v ersion	(-LW, -HW)	- 20	~ +85		°C
		temperature
				I-v ersion	(-LI, -HI)	- 40	~ +85
	T stg	Storage temperature				- 65	~ +150		°C

DC ELECTRICAL CHARACTERISTICS

* -3.0V in case of AC (Pulse width <= 30ns)

( Vcc=2.7 ~ 3.6V, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Units

Min

Ty p

Max

VIH

High-lev el input v oltage

2.2

Vcc+0.3V

VIL

Low-lev el input v oltage

-0.3 *

0.6

VOH1

High-level output voltage 1

IOH= -0.5mA

2.4

V

VOH2

High-level output voltage 2

IOH= -0.05mA

Vcc-0.5V

VOL

Low-lev el output v oltage

IOL=2mA

0.4

II

Input leakage current

VI

=0 ~ Vcc

±1

µA

IO

Output leakage current

and

±1

BC1

BC2=VIH or

S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc

Activ e supply current

BC1

and

BC2<

0.2V,

S1< 0.2V, S2

Vcc-0.2V

f = 10MHz

-

40

50

other

inputs < 0.2V

or

> Vcc-0.2V

Icc1

=

=

( AC,MOS lev el )

=

=

f = 1MHz

-

5

10

Output - open (duty

100%)

mA

-

40

50

Activ e supply current

BC1 and BC2=VIL , S=VIL ,S2=V IH

f = 10MHz

Icc2

( AC,TTL lev el )

other pins =V IH

or

VIL

f = 1MHz

-

5

10

Output - open (duty 100%)

< 1 >

-LW, -LI

+70 ~ +85°C

-

-

48

S1 => Vcc - 0.2V,

-L, -LW, -LI

+70°C

-

-

24

other inputs = 0 ~ Vcc

-HW, -HI

+70 ~ +85°C

-

-

24

< 2 >

Stand by supply current

+40 ~ +70°C

-

-

12

Icc3

S2

0.2V,

-H, -HW, -HI

µA

( AC,MOS lev el )

other inputs = 0 ~ Vcc

+25 ~ +40°C

-

1

3.6

< 3 >

-H

0 ~ +25°C

-

0.3

1.2

> Vcc - 0.2V

BC1

and

BC2

-

0.3

1.2

=

-HW

- 20 ~ +25°C

S1 =< 0.2V, S2 => Vcc - 0.2V

-HI

- 40 ~ +25°C

-

0.3

1.2

Other inputs=0~Vcc

Icc4

Stand by supply current

BC1 and BC2=VIH or S1=VIH or S2=VIL

-

-

0.5

mA

( AC,TTL lev el )

Other inputs= 0 ~ Vcc

Note 1: Direction for current flowing into IC is indicated as positive (no mark)

* -3.0V in case of AC (Pulse width < 30ns)

Note 2: Typical value is for Vcc=3.0V and Ta=25°C

=

CAPACITANCE

(Vcc=2.7 ~ 3.6V, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Units

Min

Ty p

Max

CI

Input capacitance

VI=GND, VI=25mVrms, f =1MHz

10

pF

CO

Output capacitance

VO=GND,VO=25mVrms, f =1MHz

10

MITSUBISHI ELECTRIC

3

revision-P04, ' 98.12.16

MITSUBISHI LSIs

M5M5V416BTP,RT

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS

(Vcc=2.7 ~ 3.6V, unless otherwise noted)

(1) TEST CONDITIONS

Supply v oltage

2.7V~3.6V

1TTL

Input pulse

VIH=2.4V,VIL=0.4V

DQ

Input rise time and f all time

5ns

CL

Ref erence lev el

VOH=VOL=1.5V

Transition is measured ±500mV f rom

Including scope and

steady state voltage.(f or ten,tdis)

jig capacitance

Output loads

Fig.1,CL=30pF

Fig.1 Output load

CL=5pF (for ten,tdis)

(2) READ CYCLE

Limits

Symbol

Parameter

70L,70H,70LW

85L,85H,85LW

10L,10H,10LW

Units

70HW,70LI,70HI

85HW,85LI,85HI

10HW,10LI,10HI

Min

Max

Min

Max

Min

Max

tCR

Read cy cle time

70

85

100

ns

ta(A)

Address access time

70

85

100

ns

ta(S1)

Chip select 1 access time

70

85

100

ns

a

Chip select 2 access time

70

85

100

ns

t (S2)

a

By te control 1 access time

70

85

100

ns

t (BC1)

ta(BC2)

By te control 2 access time

70

85

100

ns

ta(OE)

Output enable access time

35

45

50

ns

tdis(S1)

Output disable time af t er

25

30

35

ns

S1 high

tdis(S2)

Output disable time af t er S2 low

25

30

35

ns

tdis(BC1)

Output disable time af t er BC1 high

25

30

35

ns

tdis(BC2)

Output disable time af t er BC2 high

25

30

35

ns

tdis(OE)

Output disable time af t er OE high

25

30

35

ns

ten(S1)

Output enable time af ter

S1 low

10

10

10

ns

ten(S2)

Output enable time af ter S2 high

10

10

10

ns

ten(BC1)

Output enable time af ter BC1 low

10

10

10

ns

ten(BC2)

Output enable time af ter BC2 low

10

10

10

ns

ten(OE)

Output enable time af ter OE low

5

5

ns

tV(A)

Data v alid time after address

10

10

10

ns

(3) WRITE CYCLE

Limits

Symbol

Parameter

70L,70H,70LW

85L,85H,85LW

10L,10H,10LW

Units

70HW,70LI,70HI

85HW,85LI,85HI

10HW,10LI,10HI

Min

Max

Min

Max

Min

Max

tCW

Write cy cle time

70

85

100

ns

tw(W)

Write pulse width

55

60

75

ns

tsu(A)

Address setup time

0

0

0

ns

tsu(A-WH)

Address setup time with respect to

65

70

85

ns

W

tsu(BC1)

By te control 1 setup time

65

70

85

ns

tsu(BC2)

By te control 2 setup time

65

70

85

ns

tsu(S1)

Chip select 1 setup time

65

70

85

ns

tsu(S2)

Chip select 2 setup time

65

70

85

ns

tsu(D)

Data setup time

35

35

40

ns

th(D)

Data hold time

0

0

0

ns

trec(W)

Write recov ery time

0

0

0

ns

tdis(W)

Output disable time f rom

low

25

30

35

ns

W

tdis(OE)

Output disable time f rom

high

25

30

35

ns

OE

ten(W)

Output enable time f rom W high

5

5

5

ns

ten(OE)

5

ns

Output enable time f rom

OE

low

5

5

MITSUBISHI ELECTRIC

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