Mitsubishi M5M44800CTP-5S, M5M44800CTP-5, M5M44800CJ-7S, M5M44800CJ-7, M5M44800CJ-6S Datasheet

MITSUBISHILSIsLSIs

M5M44800CJ,TP-5,-6,--7,5,-5S,-6,-6S,-7,-7S

-5S,-6S,-7S

FASTFASTPAGEPAGEMODEMODE4194304-BIT-BIT(5242884288-WORD-WORDBYBY8-BIT)8-BIT)DYNAMICRAMRAM

DESCRIPTION

This is a family of 524288-word by 8-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential.

The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.

FEATURES

RAS

CAS

Address

OE

Cycle

Power

Type name

access

access

access

access

dissipa-

time

time

time

time

time

(min.ns)

tion

(max.ns)

(max.ns)

(max.ns)

(max.ns)

(typ.mW)

M5M44800CXX-5,-5S

50

13

25

13

90

450

M5M44800CXX-6,-6S

60

15

30

15

110

375

M5M44800CXX-7,-7S

70

20

35

20

130

325

XX=J,TP

Standard 28pin SOJ, 28pin TSOP (II)

Single 5V±10% supply

Low stand-by power dissipation

CMOS lnput level

5.5mW (Max)

CMOS Input level

550µW (Max) *

Operating power dissipation

M5M44800Cxx-5,-5S

495mW (Max)

M5M44800Cxx-6,-6S

413mW (Max)

M5M44800Cxx-7,-7S

358mW (Max)

Self refresh capability *

Self refresh current

150µA(Max)

Extended refresh capability

Extended refresh current

150µA(Max)

Fast page mode(1024-column random access),Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities.

Early-write mode, CAS and OE to control output buffer impedance

1024 refresh cycles every 16.4ms (A0 ~A9) 1024 refresh cycles every 128ms (A0 ~A9) *

*:Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S :option) only

APPLICATION

Microcomputer memory, Refresh memory for CRT

PIN DESCRIPTION

			Pin name				Function
		A0~A9					Address inputs
		DQ1~DQ8					Data inputs/outputs
							Row address strobe input
		RAS
							Column address strobe input
		CAS
							Write control input
		W
							Output enable input
			OE
	Vcc						Power supply (+5V)
	Vss						Ground (0V)

PIN CONFIGURATION (TOP VIEW)

(5V)VCC									VSS(0V)
					1		28
									DQ8
DQ1					2		27
DQ2									DQ7
					3		26
DQ3									DQ6
					4		25
	DQ4								DQ5
					5		24
	NC
					6		23
											CAS
					7		22		OE
		W
										NC
	RAS				8		21
		A9			9				A8
							20
		A0			10				A7
							19
		A1					18
					11				A6
		A2
					12		17		A5
		A3
							16		A4
					13
(5V)VCC							15		VSS(0V)
					14

Outline 28P0K(400mil SOJ)

(5V)VCC									VSS(0V)
					1		28
DQ1									DQ8
					2		27
DQ2									DQ7
					3		26
DQ3									DQ6
					4		25
	DQ4								DQ5
					5		24
	NC
					6		23
											CAS
					7		22			OE
		W
										NC
	RAS				8		21
		A9			9				A8
							20
		A0			10				A7
							19
		A1					18		A6
					11
		A2							A5
					12		17
		A3
							16		A4
					13
(5V)VCC							15		VSS(0V)
					14

Outline 28P3Y-H(400mil TSOP Normal Bend)

NC:NO CONNECTION

1

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

FUNCTION

In addition to normal read, write, and read-modify-write operations the M5M44800CJ, TP provides a number of other functions, e.g.,

Table 1 Input conditions for each mode

fast page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.

Operation

Inputs

Input/Output

Refresh

Remark

RAS

Row

Column

Input

Output

CAS

W

OE

address

address

Read

ACT

ACT

NAC

ACT

APD

APD

OPN

VLD

YES

Fast page

Write (Early write)

ACT

ACT

ACT

DNC

APD

APD

VLD

OPN

YES

mode

Write (Delayed write)

ACT

ACT

ACT

DNC

APD

APD

VLD

IVD

YES

identical

Read-modify-write

ACT

ACT

ACT

ACT

APD

APD

VLD

VLD

YES

only refresh

ACT

NAC

DNC

DNC

APD

DNC

DNC

OPN

YES

RAS

Hidden refresh

ACT

ACT

DNC

ACT

DNC

DNC

OPN

VLD

YES

before

(Extended *) refresh

ACT

ACT

DNC

DNC

DNC

DNC

DNC

OPN

YES

CAS

RAS

Self refresh *

ACT

ACT

DNC

DNC

DNC

DNC

DNC

OPN

YES

Stand-by

NAC

DNC

DNC

DNC

DNC

DNC

DNC

OPN

NO

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open

BLOCK DIAGRAM
COLUMN ADDRESS							VCC (5V)
STROBE INPUT CAS					CLOCK GENERATOR		VCC (5V)
ROW ADDRESS RAS					CIRCUIT
STROBE INPUT							VSS (0V)
WRITE CONTROL	W						VSS (0V)
INPUT
			A0~A8			(8)
					COLUMN DECODER	DATA IN	DQ1
						BUFFER
	A0						DQ2
	A1				SENSE REFRESH		DQ3
	A2						DQ4	DATA
					AMPLIFIER & I /O CONTROL
	A3						DQ5	INPUTS / OUTPUTS
		ROW &
	A4						DQ6
ADDRESS INPUTS		COLUMN
	A5	ADDRESS					DQ7
						(8)
	A6	BUFFER	A0~	ROW	MEMORY CELL		DQ8
					(4194304BITS)	DATA OUT
	A7		A9	DECODER		BUFFER
	A8
	A9						OE OUTPUT ENABLE
							INPUT
2
M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Conditions

Ratings

Unit

VCC

Supply voltage

-1~7

V

VI

Input voltage

With

respect to

VSS

-1~7

V

VO

Output

voltage

-1~7

V

IO

Output

current

50

mA

Pd

Power dissipation

Ta=25˚C

1000

mW

Topr

Operating temperature

0~70

˚C

Tstg

Storage temperature

-65~150

˚C

RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)

Symbol

Parameter

Limits

Unit

Min

Nom

Max

VCC

Supply

voltage

4.5

5.0

5.5

V

VSS

Supply voltage

0

0

0

V

VIH

High-level input voltage, all inputs

2.4

6.0

V

VIL

Low-level input voltage, all inputs

-0.5 * *

0.8

V

Note 1 : All voltage values are with respect to Vss.

* * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to VSS.)

ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted) (Note 2)

Symbol

Parameter

Test conditions

Limits

Unit

Min

Typ

Max

VOH

High-level output voltage

IOH=-5mA

2.4

Vcc

V

VOL

Low-level output voltage

IOL=4.2mA

0

0.4

V

IOZ

Off-state output current

Q floating, 0V £ VOUT £ 5.5V

-10

10

µA

I I

Input current

0V £ VIN £ +6.0V, Other inputs pins=0V

-10

10

µA

M5M44800C-5,-5S

90

ICC1 (AV)

Average supply current

RAS, CAS cycling

mA

M5M44800C-6,-6S

75

from VCC, operating

tRC=tWC=min.

(Note 3,4,5)

M5M44800C-7,-7S

output open

65

=VIH, output open

2

ICC2

Supply current from VCC, stand-by

(Note 6)

RAS=

CAS

1.0

mA

RAS= CAS ³ VCC -0.5V

output open

0.1

*

Average supply current

M5M44800C-5,-5S

90

ICC3 (AV)

RAS

cycling,

CAS= VIH

mA

M5M44800C-6,-6S

75

from VCC,

RAS

only

tRC=min.

refresh mode

(Note 3,5)

M5M44800C-7,-7S

output open

65

M5M44800C-5,-5S

90

Average supply current

RAS=VIL, CAS cycling

mA

ICC4(AV)

M5M44800C-6,-6S

75

from VCC, Fast Page

tPC=min.

Mode

(Note 3,4,5)

M5M44800C-7,-7S

output open

65

Average supply current

M5M44800C-5,-5S

before

refresh cycling

80

ICC6(AV)

CAS

RAS

from VCC,

before

M5M44800C-6,-6S

65

CAS

RAS

tRC=min.

mA

refresh mode

(Note 3,5)

M5M44800C-7,-7S

output open

55

cycling

£ 0.2V or

RAS

CAS

CAS

before

RAS

refresh cycling

£ 0.2V or ³ VCC-0.2V

RAS

ICC8(AV) *

Average supply current from VCC,

(Note 6)

CAS

£ 0.2V or ³ VCC-0.2V

150

µA

Extended-Refresh mode

W £ 0.2V or ³ VCC-0.2V

OE

£ 0.2V or ³ VCC-0.2V

A0~A9 £ 0.2V or ³ VCC-0.2V, DQ=open

tRC=125µs, tRAS=tRASmin~1µs

Average supply current from VCC,

ICC9(AV) *

(Note 6)

RAS=CAS £ 0.2V

150

µA

Self-Refresh mode

output open

Note 2: Current flowing into an IC is positive, out is negative.

3:ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.

4:ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.

5:Column address can be changed once or less while RAS=VIL and CAS=VIH

3

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

CAPACITANCE (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted)

Symbol

Parameter

Test

conditions

Limits

Unit

Min

Typ

Max

CI (A)

Input capacitance, address inputs

VI=VSS

5

pF

CI (CLK)

Input capacitance, clock inputs

f=1MHz

7

pF

CI / O

Input/Output capacitance, data ports

VI=25mVrms

7

pF

SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC = 5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tCAC

Access time from

(Note 7,8)

13

15

20

ns

CAS

tRAC

Access time from

(Note 7,9)

ns

RAS

50

60

70

tAA

Column address access time

(Note 7,10)

25

30

35

ns

tCPA

Access time from

precharge

(Note 7,11)

30

35

40

ns

CAS

tOEA

Access time from

(Note 7)

13

15

20

ns

OE

tCLZ

Output low impedance time from

low

(Note 7)

ns

CAS

5

5

5

tOFF

(Note 12)

13

ns

Output disable time after

CAS

high

15

20

tOEZ

Output disable time after

high

(Note 12)

13

15

20

ns

OE

Note 6:An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles).

Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of RAS inactivity before proper device operation is achieved.

7:Measured with a load circuit equivalent to 2TTL loads and 100pF. 8:Assumes that tRCD ³ tRCD(max) and tASC ³ tASC(max).

9:Assumes that tRCD £ tRCD(max) and tRAD £ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown.

10:Assumes that tRAD ³ tRAD(max) and tASC £ tASC(max). 11:Assumes that tCP £ tCP(max) and tASC ³ tASC(max).

12:tOFF(max), tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT £ ±10µA ) and is not reference to V OH(min) or VOL(max).

4

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)

(Ta=0~70˚C, VCC = 5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tREF

Refresh cycle time

16.4

16.4

16.4

ms

tREF

Refresh cycle time *

128

128

128

ms

tRP

high pulse width

30

40

50

ns

RAS

tRCD

Delay time,

low to

low

(Note 15)

18

37

20

45

20

50

ns

RAS

CAS

tCRP

Delay time,

high to

low

5

5

5

ns

CAS

RAS

tRPC

Delay time,

high to

low

0

0

0

ns

RAS

CAS

tCPN

high pulse width

10

10

10

ns

CAS

tRAD

Column address delay time from

low

(Note 16)

13

25

15

30

15

35

ns

RAS

tASR

Row address setup time before

low

0

0

0

ns

RAS

tASC

Column address setup time before

low

(Note 17)

0

7

0

10

0

10

ns

CAS

tRAH

Row address hold time after

low

8

10

10

ns

RAS

tCAH

Column address hold time after

low

13

15

15

ns

CAS

tDZC

(Note 18)

0

0

0

ns

Delay time, data to

CAS

low

tDZO

(Note 18)

0

0

0

ns

Delay time, data to

OE

low

tCDD

Delay time,

high to data

(Note 19)

13

15

20

ns

CAS

tODD

Delay time,

high to data

(Note 19)

13

15

20

ns

OE

tT

Transition time

(Note 20)

1

50

1

50

1

50

ns

Note 13: The timing requirements are assumed tT=5ns.

14:VIH(min) and VIL(max) are reference levels for measuring timing of input signals.

15:tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA.

16:tRAD(max) is specified as a reference point only. If tRAD ³ tRAD(max) and tASC £ tASC(max), access time is controlled exclusively by tAA.

17:tASC(max) is specified as a reference point only. If tRCD ³ tRCD(max) and tASC ³ tASC(max), access time is controlled exclusively by tCAC.

18:Either tDZC or tDZO must be satisfied.

19:Either tCDD or tODD must be satisfied.

20:tT is measured between VIH(min) and VIL(max).

Read and Refresh Cycles

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRC

Read cycle time

90

110

130

ns

tRAS

low pulse width

50

10000

60

10000

70

10000

ns

RAS

tCAS

13

10000

15

10000

20

10000

ns

CAS low pulse width

tCSH

50

60

70

ns

CAS

hold time after RAS low

tRSH

hold time after

low

13

15

20

ns

RAS

CAS

tRCS

Read Setup time before

low

0

0

0

ns

CAS

tRCH

Read hold time after

high

(Note 21)

0

0

0

ns

CAS

tRRH

Read hold time after

high

(Note 21)

0

0

0

ns

RAS

tRAL

Column address to

hold time

25

30

35

ns

RAS

tOCH

hold time after

low

13

15

20

ns

CAS

OE

tORH

hold time after

low

13

15

20

ns

RAS

OE

Note 21: Either tRCH or tRRH must be satisfied for a read cycle.

5

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

Write Cycle (Early Write and Delayed Write)

Limits

Symbol

Parameter

Unit

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Min

Max

Min

Max

Min

Max

tWC

Write cycle time

90

110

130

ns

tRAS

low pulse width

50

10000

60

10000

70

10000

RAS

ns

tCAS

low pulse width

13

10000

15

10000

20

10000

ns

CAS

tCSH

hold time after

low

50

60

70

ns

CAS

RAS

tRSH

hold time after

low

13

15

20

ns

RAS

CAS

tWCS

Write setup time before

low

(Note 23)

0

0

0

ns

CAS

tWCH

Write hold time after

low

8

10

15

ns

CAS

tCWL

hold time after

low

13

15

20

ns

CAS

W

tRWL

13

15

20

ns

RAS hold time after W low

tWP

Write pulse width

8

10

15

ns

tDS

Data setup time before

low or

low

0

0

0

ns

CAS

W

tDH

Data hold time after

low or

low

8

10

15

ns

CAS

W

tOEH

13

15

20

ns

OE hold time after W low

Read-Write and Read-Modify-Write Cycles

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRWC

Read write/read modify write cycle time

(Note 22)

126

150

180

ns

tRAS

86

10000

100

10000

120

10000

ns

RAS low pulse width

tCAS

low pulse width

49

10000

55

10000

70

10000

ns

CAS

tCSH

hold time after

low

86

100

120

CAS

RAS

ns

tRSH

hold time after

low

49

55

70

ns

RAS

CAS

tRCS

Read setup time before

low

0

0

0

ns

CAS

tCWD

Delay time,

low to

low

(Note 23)

31

35

45

ns

CAS

W

tRWD

Delay time,

low to

low

(Note 23)

68

80

95

ns

RAS

W

tAWD

Delay time, address to

low

(Note 23)

43

50

60

ns

W

tCWL

13

15

20

ns

CAS hold time after

W

low

tRWL

hold time after

low

13

15

20

ns

RAS

W

tWP

Write pulse width

8

10

15

ns

tDS

0

0

0

ns

Data setup time before CAS low or

W

low

tDH

ns

Data hold time after CAS low or

W

low

8

10

15

tOEH

13

15

20

ns

OE hold time after W low

Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.

Note 23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ³ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ³ tCWD(min), tRWD ³ tRWD(min), tAWD ³ tAWD(min) and tCPWD ³ tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.

6

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

Fast Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 24)

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tPC

Fast page mode read/write cycle time

35

40

45

ns

tPRWC

Fast page mode read write/read modify write cycle time

71

80

95

ns

tRAS

low pulse width for read or write cycle

(Note 25)

85

100000

100

100000

115

100000

ns

RAS

tCP

high pulse width

(Note 26)

8

12

10

15

10

15

ns

CAS

tCPRH

hold time after

precharge

30

35

40

ns

RAS

CAS

tCPWD

Delay time,

precharge to

low

(Note 23)

48

55

65

ns

CAS

W

Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.

Note 25: tRAS(min) is specified as two cycles of CAS input are performed.

Note 26: tCP(max) is specified as a reference point only.

CAS before RAS Refresh Cycle, Extended Refresh Cycle *

(Note 27)

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tCSR

setup time before

low

5

5

5

ns

CAS

RAS

tCHR

hold time after

low

10

10

15

ns

CAS

RAS

low pulse width

20

20

25

ns

tCAS

CAS

Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.

Self Refresh Cycle * (Note 28)

Limits

Symbol

Parameter

M5M44800C-5,-5S

M5M44800C-6,-6S

M5M44800C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRASS

CBR self refresh

low pulse width

100

100

100

µs

RAS

tRPS

CBR self refresh

high precharge time

90

110

130

ns

RAS

tCHS

CBR self refresh

hold time

-50

-50

-50

ns

CAS

7

M5M44800CJ,TP-5,-5S:Under development