Mitsubishi M5M44260CTP-7S, M5M44260CTP-7, M5M44260CTP-6S, M5M44260CTP-6, M5M44260CTP-5S Datasheet

MITSUBISHIMITSUBISHILSIsLSIs

M5M44260CJ,TP-5,-6,--7,5,-5S,-6,-6S,-7,-7S

-5S,-6S,-7S

FASTFASTPAGEPAGEMODEMODE4194304304-BIT-BIT(262144(262144-WORD-WORDBY BY16-BIT)16-BIT)DYNAMICDYNAMICRAMRAM

DESCRIPTION

This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential.

The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is small enough for battery back-up application.

This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.

FEATURES

Power

RAS

CAS

Address

OE

Cycle

Type name

access

access

access

access

time

dissipa-

time

time

time

time

tion

(max.ns)

(max.ns)

(max.ns)

(max.ns)

(min.ns)

(typ.mW)

M5M44260CXX-5,-5S

50

13

25

13

90

625

M5M44260CXX-6,-6S

60

15

30

15

110

550

M5M44260CXX-7,-7S

70

20

35

20

130

475

XX=J,TP

Standard 40pin SOJ, 44 pin TSOP (II)

Single 5V±10% supply

Low stand-by power dissipation

CMOS Input level

5.5mW (Max)

CMOS Input level

550µW (Max) *

Operating power dissipation

M5M44260Cxx-5,-5S

688mW (Max)

M5M44260Cxx-6,-6S

605mW (Max)

M5M44260Cxx-7,-7S

523mW (Max)

Self refresh capability *

Self refresh current

150µA (Max)

Extended refresh capability

Extended refresh current

150µA (Max)

Fast-page mode (512-column random access), Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities.

Early-write mode, LCAS / UCAS and OE to control output buffer impedance

512 refresh cycles every 8.2ms (A0~A8) 512 refresh cycles every 128ms (A0~A8) *

Byte or word control for Read/Write operation (2CAS, 1W type)

*: Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S

:option) only

APPLICATION

Microcomputer memory, Refresh memory for CRT

PIN DESCRIPTION

			Pin name						Function
			A0~A8						Address inputs
	DQ1~DQ16								Data inputs / outputs
									Row address strobe input
	RAS
									Lower byte control
	LCAS
									column address strobe input
									Upper byte control
	UCAS
									column address strobe input
									Write control input
		W
									Output enable input
			OE
	VCC								Power supply (+5V)
			VSS						Ground (0V)

1	M5M44260CJ,TP-5,-5S : Under development

PIN CONFIGURATION (TOP VIEW)

(5V)VCC														VSS(0V)
							1					40
	DQ1													DQ16
							2					39
	DQ2													DQ15
							3					38
	DQ3													DQ14
							4					37
	DQ4													DQ13
							5					36
(5V)VCC														VSS(0V)
							6					35
	DQ5													DQ12
							7					34
	DQ6													DQ11
							8					33
	DQ7													DQ10
							9					32
	DQ8													DQ9
							10					31
	NC													NC
							11					30
	NC
							12					29		LCAS
		W					13					28		UCAS
	RAS						14					27		OE
	NC						15					26		A8
		A0												A7
							16					25
		A1												A6
							17					24
		A2
							18					23		A5
		A3
							19					22		A4
														VSS(0V)
(5V)VCC							20					21
	Outline 40P0K (400mil SOJ)
(5V)VCC														VSS(0V)
							1					44
	DQ1
							2					43		DQ16
	DQ2
							3					42		DQ15
														DQ14
	DQ3						4					41
	DQ4													DQ13
							5					40
(5V)VCC							6					39		VSS(0V)
	DQ5													DQ12
							7					38
														DQ11
	DQ6						8					37
	DQ7													DQ10
							9					36
	DQ8													DQ9
							10					35
	NC													NC
							13					32
	NC
							14					31		LCAS
		W					15					30		UCAS
	RAS						16					29		OE
	NC						17					28		A8
		A0					18					27		A7
		A1					19					26		A6
		A2					20					25		A5
														A4
		A3					21					24
(5V)VCC							22					23		VSS(0V)

Outline 44P3W-R (400mil TSOP Nomal Bend)

NC: NO CONNECTION

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

FUNCTION

In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g.,

Table 1 Input conditions for each mode

fast page mode, RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1.

Operation

Inputs

Input/Output

Refresh

Remark

Row

Column

DQ1~

DQ9~

RAS

LCAS

UCAS

W

OE

address

address

DQ8

DQ16

Lower byte read

ACT

ACT

NAC

NAC

ACT

APD

APD

DOUT

OPN

YES

Upper byte read

ACT

NAC

ACT

NAC

ACT

APD

APD

OPN

DOUT

YES

Fast

Word read

ACT

ACT

ACT

NAC

ACT

APD

APD

DOUT

DOUT

YES

page

Lower byte write

ACT

ACT

NAC

ACT

NAC

APD

APD

DIN

DNC

YES

mode

identical

Upper byte write

ACT

NAC

ACT

ACT

NAC

APD

APD

DNC

DIN

YES

Word write

ACT

ACT

ACT

ACT

NAC

APD

APD

DIN

DIN

YES

only refresh

NAC

NAC

DNC

DNC

APD

DNC

OPN

YES

RAS

ACT

OPN

Hidden refresh

ACT

ACT

ACT

DNC

ACT

DNC

DNC

DOUT

DOUT

YES

ACT

ACT

ACT

DNC

DNC

DNC

DNC

OPN

OPN

YES

CAS

before RAS (Extended *) refresh

Self refresh *

ACT

ACT

ACT

DNC

DNC

DNC

DNC

OPN

OPN

YES

Stand-by

NAC

DNC

DNC

DNC

DNC

DNC

DNC

OPN

OPN

No

Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open

BLOCK DIAGRAM

ROW ADDRESS							VCC (5V)
STROBE INPUT	RAS				CLOCK GENERATOR
LOWER BYTE CONTROL	LCAS						VSS (0V)
COLUMN ADDRESS					CIRCUIT
STROBE INPUT					LOWER	(8)LOWER
UPPER BYTE CONTROL UCAS
						DATA IN	DQ1
COLUMN ADDRESS						BUFFER		LOWER DATA
STROBE INPUT					UPPER		DQ2
WRITE CONTROL								INPUTS /
	W
								OUTPUTS
INPUT							DQ8
						(8)LOWER
						DATA OUT	VCC (5V)
						BUFFER
							VSS (0V)
			A0~A8
					COLUMN DECODER	(8)UPPER
						DATA IN
	A0				SENSE REFRESH	BUFFER	DQ9	UPPER DATA
	A1						DQ10
	A2				AMPLIFIER & I /O CONTROL			INPUTS /
								OUTPUTS
	A3	ROW &					DQ16
						(8)UPPER
ADDRESS INPUTS	A4	COLUMN
						DATA OUT
		ADDRESS
	A5				MEMORY CELL	BUFFER
		BUFFER	A0~	ROW
					(4194304 BITS)
	A6
			A8	DECODER
	A7
							VCC (5V)
	A8
							VSS (0V)

OUTPUT ENABLE

OE INPUT

2 M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Conditions

Ratings

Unit

VCC

Supply voltage

-1~7

V

V I

Input voltage

With respect to VSS

-1~7

V

VO

Output voltage

-1~7

V

I O

Output current

50

mA

Pd

Power dissipation

Ta=25˚C

1000

mW

Topr

Operating temperature

0~70

˚C

Tstg

Storage temperature

-65~150

˚C

RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)

Symbol

Parameter

Limits

Unit

Min

Nom

Max

VCC

Supply voltage

4.5

5.0

5.5

V

VSS

Supply voltage

0

0

0

V

VIH

High-level input voltage, all inputs

2.4

6.0

V

VIL

Low-level input voltage, all inputs

-0.5 * *

0.8

V

Note 1 : All voltage values are with respect to

VSS.

* * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.)

ELECTRICAL CHARACTERISTICS (Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted) (Note 2)

Symbol

Parameter

Test

conditions

Limits

Unit

Min

Typ

Max

VOH

High-level output voltage

IOH=-5mA

2.4

VCC

V

VOL

Low-level output voltage

IOL=4.2mA

0

0.4

V

IOZ

Off-state output current

Q floating 0V £ VOUT £ 5.5V

-10

10

µA

I I

Input current

0V £ VIN £ +6.0V, Other inputs pins=0V

-10

10

µA

Average supply current

M5M44260C-5,-5S

125

RAS, CAS cycling

ICC1(AV)

from Vcc, operating

M5M44260C-6,-6S

tRC=tWC=min.

110

mA

(Note 3,4,5)

output open

M5M44260C-7,-7S

95

2

RAS= CAS =VIH, output open

ICC2

Supply current from VCC, stand-by (Note 6)

³ VCC -0.5V

1.0

mA

RAS=

CAS

output open

0.1

*

Average supply current

M5M44260C-5,-5S

125

RAS cycling, CAS=VIH

ICC3(AV)

from Vcc, RAS only

M5M44260C-6,-6S

110

mA

tRC=min.

refresh mode

output open

M5M44260C-7,-7S

95

(Note 3,5)

Average supply current

M5M44260C-5,-5S

125

RAS=VIL, CAS cycling

from Vcc

M5M44260C-6,-6S

110

mA

ICC4(AV)

tPC=min.

Fast page mode

output open

(Note 3,4,5)

M5M44260C-7,-7S

95

Average supply current

M5M44260C-5,-5S

115

CAS before RAS refresh cycling

from Vcc

ICC6(AV)

M5M44260C-6,-6S

tRC=min.

100

mA

CAS

before RAS refresh

mode

(Note 3,5)

M5M44260C-7,-7S

output open

85

cycling

£ 0.2V or

RAS

CAS

CAS

before RAS refresh cycling

RAS £ 0.2V or ³ VCC-0.2V

Average supply current

CAS £ 0.2V or ³ VCC-0.2V

ICC8(AV) *

from VCC

W £ 0.2V or ³ VCC-0.2V

150

µA

Extended-refresh mode

(Note 6)

OE £ 0.2V or ³ VCC-0.2V

A0~A8 £ 0.2V or ³ VCC-0.2V,

DQ=open

tRC=250µs, tRAS=tRAS min~1µs

ICC9(AV) *

Average supply current from VCC

RAS=CAS £ 0.2V

150

µA

Self-refresh mode

(Note 6)

output open

Note 2: Current flowing into an IC is positive, out is negative.

3:ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.

4:ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.

	3		5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
		M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

CAPACITANCE (Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted)

Symbol

Parameter

Test

conditions

Limits

Unit

Min

Typ

Max

CI (A)

Input capacitance, address inputs

VI=VSS

5

pF

CI (CLK)

Input capacitance, clock inputs

f=1MHz

7

pF

CI / O

Input/Output capacitance, data ports

VI=25mVrms

7

pF

SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=5V±10%, Vss=0V, unless otherwise noted, see notes 6,13,14)

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tCAC

(Note 7,8)

13

15

20

ns

Access time from

CAS

tRAC

(Note 7,9)

ns

Access time from

RAS

50

60

70

tAA

Columu address access time

(Note 7,10)

25

30

35

ns

tCPA

(Note 7,11)

30

35

40

ns

Access time from

CAS

precharge

tOEA

(Note 7)

13

15

20

ns

Access time from

OE

tCLZ

Output low impedance time from

low

(Note 7)

5

5

5

CAS

ns

Output disable time after

high

(Note 12)

13

15

20

tOFF

CAS

ns

tOEZ

Output disable time after

high

(Note 12)

13

15

20

ns

OE

Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles).

Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved.

7:Measured with a load circuit equivalent to 2TTL loads and 100pF.

8:Assumes that tRCD ³ tRCD(max) and tASC ³ tASC(max).

9:Assumes that tRCD £ tRCD(max) and tRAD £ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown.

10:Assumes that tRAD ³ tRAD(max) and tASC £ tASC(max).

11:Assumes that tCP £ tCP(max) and tASC ³ tASC(max).

12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT £ ±10 µA ) and is not reference to V OH(min) or VOL(max).

4 M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles)

(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tREF

Refresh cycle time

8.2

8.2

8.2

ms

tREF

Refresh cycle time *

128

128

128

ms

tRP

high pulse width

30

40

50

ns

RAS

tRCD

Delay time,

low to

low

(Note 15)

18

37

20

45

50

RAS

CAS

20

ns

5

tCRP

Delay time,

CAS

high to

RAS

low

5

5

ns

tRPC

Delay time,

high to

low

0

0

0

ns

RAS

CAS

tCPN

high pulse width

10

10

ns

CAS

10

Column address delay time from

low

13

ns

tRAD

RAS

(Note 16)

25

15

30

15

35

tASR

Row address setup time before

RAS

low

0

0

0

ns

tASC

Column address setup time before

low

(Note 17)

0

7

10

0

ns

CAS

0

10

tRAH

Row address hold time after

low

8

10

10

ns

RAS

tCAH

Column address hold time after

low

13

15

15

ns

CAS

tDZC

Delay time, data to

low

(Note 18)

0

CAS

0

0

ns

tDZO

(Note 18)

0

Delay time, data to

OE

low

0

0

ns

tCDD

Delay time,

high to data

(Note 19)

13

15

20

CAS

ns

tODD

Delay time,

high to data

(Note 19)

13

OE

15

20

ns

tT

Transition time

(Note 20)

1

50

1

50

1

50

ns

Note 13: The timing requirements are assumed tT =5ns.

14:VIH(min) and VIL(max) are reference levels for measuring timing of input signals.

15:tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA.

16:tRAD(max) is specified as a reference point only. If tRAD ³ tRAD(max) and tASC £ tASC(max), access time is controlled exclusively by tAA.

17:tASC(max) is specified as a reference point only. If tRCD ³ tRCD(max) and tASC ³ tASC(max), access time is controlled exclusively by tCAC.

18:Either tDZC or tDZO must be satisfied.

19:Either tCDD or tODD must be satisfied.

20:tT is measured between VIH(min) and VIL(max).

Read and Refresh Cycles

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRC

Read cycle time

90

110

130

ns

tRAS

low pulse width

50

10000

60

10000

70

10000

ns

RAS

tCAS

low pulse width

13

15

20

ns

CAS

10000

10000

10000

tCSH

hold time after

50

60

70

ns

CAS

RAS low

tRSH

hold time after

low

13

15

20

ns

RAS

CAS

tRCS

Read setup time before

low

0

0

ns

CAS

0

tRCH

Read hold time after

(Note 21)

0

0

0

ns

CAS high

tRRH

Read hold time after

high

(Note 21)

0

0

0

ns

RAS

tRAL

Column address to

hold time

25

30

35

ns

RAS

tOCH

hold time after

low

13

15

20

ns

CAS

OE

tORH

hold time after

low

13

15

20

ns

RAS

OE

Note 21: Either tRCH or tRRH must be satisfied for a read cycle.

5

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Write Cycle (Early Write and Delayed Write)

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tWC

Write cycle time

90

110

130

ns

low pulse width

50

10000

60

10000

70

10000

ns

tRAS

RAS

low pulse width

ns

tCAS

CAS

13

10000

15

10000

20

10000

tCSH

50

60

70

ns

CAS

hold time after

RAS

low

low

13

15

20

ns

tRSH

RAS

hold time after

CAS

tWCS

Write setup time before

low

(Note 23)

CAS

0

0

0

ns

tWCH

8

10

15

ns

Write hold time after CAS low

tCWL

13

ns

CAS

hold time after

W

low

15

20

tRWL

RAS

hold time after

W

low

13

15

20

ns

tWP

Write pulse width

8

10

15

ns

tDS

0

0

ns

Data setup time before

CAS

low or

W

low

0

tDH

8

10

Data hold time after

CAS

low or

W

low

15

ns

tOEH

13

15

20

ns

OE

hold time after

W

low

Read-Write and Read-Modify-Write Cycles

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRWC

Read write/read modify write cycle time

(Note 22)

126

150

180

ns

tRAS

low pulse width

86

10000

100

10000

120

10000

ns

RAS

low pulse width

49

10000

55

10000

70

tCAS

CAS

10000

ns

tCSH

86

100

120

CAS

hold time after

RAS

low

ns

tRSH

hold time after

low

49

55

70

ns

RAS

CAS

tRCS

Read setup time before

low

0

0

0

ns

CAS

tCWD

Delay time,

low to

low

(Note 23)

31

35

45

ns

CAS

W

tRWD

Delay time,

low to

low

(Note 23)

68

80

95

ns

RAS

W

Delay time, address to

low

(Note 23)

43

50

60

tAWD

W

ns

tCWL

hold time after

low

13

15

20

ns

CAS

W

tRWL

hold time after

low

13

15

20

ns

RAS

W

tWP

Write pulse width

8

10

15

ns

tDS

Data setup time before

low or

low

0

0

0

ns

CAS

W

tDH

Data hold time after

low or

low

8

10

15

ns

CAS

W

tOEH

low

13

15

20

OE

hold time after

W

ns

Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.

23:tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ³ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ³ tCWD(min), tRWD ³ tRWD(min), tAWD ³ tAWD(min) and tCPWD ³ tCPWD(min)

(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.

6

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)

Limits

Symbol

Parameter

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tPC

Fast page mode read/write cycle time

35

40

45

ns

tPRWC

Fast page mode read write/read modify write cycle time

71

80

95

ns

low pulse width for read or write cycle

(Note 25)

85

100000

100

100000

115

100000

ns

tRAS

RAS

tCP

high pulse width

(Note 26)

8

12

10

15

10

15

ns

CAS

tCPRH

hold time after

precharge

30

35

40

ns

RAS

CAS

tCPWD

Delay time,

precharge to

low

(Note 23)

48

ns

CAS

W

55

65

Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.

25:tRAS(min) is specified as two cycles of CAS input are performed.

26:tCP(max) is specified as a reference point only.

CAS before RAS Refresh Cycle, Extended Refresh Cycle *

(Note 27)

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

setup time before

low

5

5

5

ns

tCSR

CAS

RAS

tCHR

hold time after

low

10

10

15

ns

CAS

RAS

tCAS

low pulse width

20

20

ns

CAS

25

Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.

Self Refresh Cycle * (Note 28)

Limits

Symbol

Parameter

M5M44260C-5,-5S

M5M44260C-6,-6S

M5M44260C-7,-7S

Unit

Min

Max

Min

Max

Min

Max

tRASS

CBR self refresh

low pulse width

100

100

100

µs

RAS

tRPS

CBR self refresh

high precharge time

90

110

130

ns

RAS

tCHS

CBR self refresh

hold time

-50

-50

-50

ns

CAS

7

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Timing Diagrams (Note 29)

Read Cycle

VIH

RAS

VIL

VIH

LCAS/UCAS

VIL

VIH

A0~A8

VIL

VIH

W

VIL

DQ1~DQ16 VIH

(INPUTS) V

IL

DQ1~DQ16 VOH

(OUTPUTS) VOL

VIH

OE

VIL

			tRC
		tRAS		tRP
		tCSH
tCRP		tRCD	tRSH	tRPC
			tCAS	tCRP
		tRAD	tRAL
tASR	tRAH	tCAH		tASR
		tASC
	ROW	COLUMN		ROW
ADDRESS		ADDRESS		ADDRESS
			tRCH	tRRH
		tRCS
		tDZC		tCDD
			Hi-Z
		tCAC
		tAA	tOFF
		tCLZ
		Hi-Z	DATA VALID	Hi-Z
		tRAC	tOEZ
		tDZO
			tOEA	tODD
			tOCH
			tORH

Indicates the don't care input.

Note 29 ≤ ≤ ≤ ≤

VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max)

Indicates the invalid output.

8

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Byte Read Cycle

						tRC
					tRAS		tRP
	RAS	VIH
		VIL
					tCSH
		tCRP		tRCD		tRSH	tRPC	tCRP
						tCAS
	UCAS	VIH
	(or LCAS)	VIL
						tCPN
	LCAS	VIH
	(or UCAS)	VIL		tRAD		tRAL
		tASR	tRAH	tASC	tCAH			tASR
	A0~A8	VIH	ROW	COLUMN				ROW
		ADDRESS		ADDRESS				ADDRESS
		VIL
							tRRH
				tRCS		tRCH
	W	VIH
		VIL
	DQ1~DQ8	VIH
	(or DQ9~DQ16)
	(INPUTS)	VIL
	DQ1~DQ8	VOH				Hi-Z
	(or DQ9~DQ16)
	(OUTPUTS) VOL
				tDZC			tCDD
	DQ9~DQ16	VIH				Hi-Z
	(or DQ1~DQ8)
	(INPUTS)	VIL			tCAC
					tAA	tOFF
	DQ9~DQ16				tCLZ
		VOH		Hi-Z				Hi-Z
	(or DQ1~DQ8)					DATA VALID
	(OUTPUTS) VOL
				tRAC
						tOEZ
				tDZO		tOEA	tODD
						tOCH
	OE	VIH
		VIL
						tORH
9	M5M44260CJ,TP-5,-5S : Under development