Mitsubishi M5M5V208KR-10LL, M5M5V208KR-10L, M5M5V208FP-85LL, M5M5V208FP-85L, M5M5V208FP-70LL Datasheet

'97.3.21	MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR	-70L , -85L, -10L , -12L,
	-70LL, -85LL, -10LL, -12LL

2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM

DESCRIPTION

The M5M5V208 is 2,097,152-bit CMOS static RAM organized as 262,144-words by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor(TFT) load cells and CMOS periphery results in a high density and low power static RAM. The M5M5V208 is designed for memory applications where high reliability, large storage, simple interfacing and battery back-up are important design objectives.

The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available.

VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.

FEATURE

					Access		Power supply current
	Type				time		Active	Stand-by
					(max)
							(max)	(max)
M5M5V208FP,VP,RV,KV,KR-70L					70ns
M5M5V208FP,VP,RV,KV,KR-85L					85ns			60µA
M5M5V208FP,VP,RV,KV,KR-10L					100ns
								(Vcc=3.6V)
M5M5V208FP,VP,RV,KV,KR-12L				120ns			27mA
M5M5V208FP,VP,RV,KV,KR-70LL					70ns		(Vcc=3.6V)
M5M5V208FP,VP,RV,KV,KR-85LL					85ns			10µ A
M5M5V208FP,VP,RV,KV,KR-10LL					100ns
								(Vcc=3.6V)
M5M5V208FP,VP,RV,KV,KR-12LL					120ns
• Single 2.7 ~ 3.6V power			supply
• Operating temperature of			0 to +70°C
• No	clocks, No	refresh
• All	inputs and	outputs are TTL			compatible.

•Easy memory expansion and power down by S1 & S2

•Data retention supply voltage=2.0V

• Three-state outputs: OR-tie capability

• OE prevents data contention in the I/O bus

•Common Data I/O

•Battery backup capability

•Small stand-by current · · · · · · · · · · 0.3µA(typ.)

PACKAGE

M5M5V208FP : 32 pin 525 mil SOP
M5M5V208VP,RV : 32pin	8 X	20 mm2	TSOP
M5M5V208KV,KR : 32pin	8 X	13.4 mm2	TSOP

APPLICATION

Small capacity memory units

Battery operating system

Handheld communiation tools

		PIN CONFIGURATION (TOP VIEW)
		A17	1	32	VCC(3V)
		A16	2	31	A15
		A14	3	30	S2
		A12	4	29	W
		A7	5	28	A13
		A6	6	27	A8
		A5	7	26	A9
		A4	8	25	A11
		A3	9	24	OE
		A2 10		23	A10
		A1 11		22	S1
		A0 12		21	DQ8
		DQ1 13		20	DQ7
		DQ2 14		19	DQ6
		DQ3 15		18	DQ5
	(0V)GND 16			17	DQ4
				Outline 32P2M-A(FP)
A11	1				32	OE
A9	2				31	A10
A8	3				30	S1
A13	4				29	DQ8
W	5				28	DQ7
S2	6				27	DQ6
A15	7				26	DQ5
Vcc 8			M5M5V208VP,KV		25	DQ4
A17	9				24	GND
A16	10				23	DQ3
A14	11				22	DQ2
A12	12				21	DQ1
A7	13				20	A0
A6	14				19	A1
A5	15				18	A2
A4	16				17	A3
		Outline 32P3H-E(VP), 32P3K-B(KV)
A4	16				17	A3
A5	15				18	A2
A6	14				19	A1
A7	13				20	A0
A12	12				21	DQ1
A14	11				22	DQ2
A16	10				23	DQ3
A17	9	M5M5V208RV,KR			24	GND
Vcc 8					25	DQ4
A15	7				26	DQ5
S2	6				27	DQ6
W	5				28	DQ7
A13	4				29	DQ8
A8	3				30	S1
A9	2				31	A10
A11	1				32	OE
		Outline 32P3H-F(RV), 32P3K-C(KR)

MITSUBISHI ELECTRIC

1

'97.3.21	MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR	-70L , -85L, -10L , -12L,
	-70LL, -85LL, -10LL, -12LL

2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM

FUNCTION

The operation mode of the M5M5V208 is determined by a combination of the device control inputs S1, S2, W and OE. Each mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps with the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable OE directly controls the output stage. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state (S1

=L ,S2 = H).

When setting S1 at a high level or S2 at a low level, the

chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S1 or S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode.

FUNCTION TABLE

S1			S2	W		OE		Mode	DQ	Icc
X			L	X		X		Non selection	High-impedance	Standby
H			X	X		X		Non selection	High-impedance	Standby
L			H	L		X		Write	D IN	Active
L			H	H		L		Read	D OUT	Active
L			H	H		H			High-impedance	Active

BLOCK DIAGRAM

				*				*
	A4	8	16
	A5	7	15				21	13	DQ1
	A6	6	14				22	14	DQ2
				262144		WORDS
	A7	5	13				23	15	DQ3
					X 8	BITS
	A12	4	12		512	ROWS	25	17	DQ4
	A14	3	11	X	128 COLUMNS		26	18	DQ5
				X	32	BLOCKS
	A16	2	10				27	19	DQ6
	A17	1	9				28	20	DQ7
	A15	31	7				29	21	DQ8
	A0	12	20
	A1	11	19			CLOCK
	A2
		10	18		GENERATOR
	A3	9	17
	A10	23	31				5	29	W
							30	22	S1
	A11	25	1
							6	30	S2
	A9	26	2
							32	24	OE
	A8	27	3
	A13	28	4				8	32	VCC
									(3V)
							24	16	GND
									(0V)

*Pin numbers inside dotted line show those of TSOP.

MITSUBISHI

ELECTRIC

2

'97.3.21	MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR	-70L , -85L, -10L , -12L,
	-70LL, -85LL, -10LL, -12LL

2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

	Symbol	Parameter	Conditions	Ratings		Unit
	Vcc	Supply voltage		– 0.5*~4.6		V
	VI	Input voltage	With respect to GND	– 0.5* ~ Vcc + 0.5		V
				(Max	4.6)
	VO	Output voltage		0	~ Vcc	V
	Pd	Power dissipation	Ta=25°C	700		mW
	Topr	Operating temperature		0	~ 70	°C
	Tstr	Storage temperature		– 65 ~150		°C

* –3.0V in case of AC ( Pulse width £ 30ns )

DC ELECTRICAL CHARACTERISTICS

(Ta=0~70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)

Symbol

Parameter

Test conditions

Limits

Unit

Min Typ

Max

VIH

High-level input voltage

2.0

Vcc

V

+0.3V

VIL

Low-level input voltage

–0.3*

0.6

V

VOH1

High-level output voltage 1

IOH= –0.5mA

2.4

V

VOH2

High-level output voltage 2

IOH= –0.05mA

Vcc

V

-0.5V

VOL

Low-level output voltage

IOL=2mA

0.4

V

II

Input current

VI=0 ~ Vcc

±1

µA

IO

Output current in off-state

S

1=VIH or S2=VIL or

OE=VIH

±1

µA

VI/O=0 ~ Vcc

Icc1

Active supply current

S1 £ 0.2V, S2³ Vcc-0.2V,

f= 10MHz

20

25

mA

(CMOS-level Input)

other inputs £ 0.2V

f= 5MHz

10

13

or ³ Vcc-0.2V,output-open

f= 10MHz

22

27

Icc2

Active supply current

S1=VIL,S2=VIH,

other inputs=VIH or VIL

mA

(TTL-level Input)

f= 5MHz

12

15

output-open

1) S2 £ 0.2V or

-L

-20 ~ +70°C

60

-20 ~ +70°C

10

Icc3

Stand-by current

2) S1 ³ Vcc-0.2V,

µA

S2 ³ Vcc-0.2V

-LL

-20 ~ +40°C

1

other inputs=0 ~ Vcc

+25°C

0.3

0.6

Icc4

Stand-by current

1=VIH or S2=VIL,other inputs=0 ~ Vcc

0.33

mA

S

* –3.0V in case of AC ( Pulse width £ 30ns )

	CAPACITANCE		(Ta=0 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
	Symbol	Parameter	Test conditions		Limits		Unit
				Min	Typ	Max
	CI	Input capacitance	VI=GND, VI=25mVrms, f=1MHz			7	pF
	CO	Output capacitance	VO=GND,VO=25mVrms, f=1MHz			9	pF

Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is for Vcc = 3V, Ta = 25°C

MITSUBISHI

ELECTRIC

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