Mitsubishi M5M51008BKV-12VLL, M5M51008BKV-12VL, M5M51008BKV-10VLL, M5M51008BKV-10VL, M5M51008BFP-10VL Datasheet

1997-1/21 MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

DESCRIPTION

The M5M51008BFP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM.

They are low standby current and low operation current and ideal for the battery back-up application.

The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available.

VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.

FEATURES

		Access				Power supply current
Type name		time	VCC				Active	stand-by
		(max)				(1MHz)		(max)
							(max)
M5M51008BFP,VP,RV,KV,KR-70VL		70ns	3.3±0.3V				10mA	60µA
M5M51008BFP,VP,RV,KV,KR-10VL		100ns
M5M51008BFP,VP,RV,KV,KR-12VL		120ns	3.0±0.3V				10mA	55µA
M5M51008BFP,VP,RV,KV,KR-15VL		150ns
M5M51008BFP,VP,RV,KV,KR-70VLL		70ns	3.3±0.3V				10mA	12µA
M5M51008BFP,VP,RV,KV,KR-10VLL		100ns
M5M51008BFP,VP,RV,KV,KR-12VLL		120ns	3.0±0.3V				10mA	11µA
M5M51008BFP,VP,RV,KV,KR-15VLL		150ns
Low stand-by current 0.3µA (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by					1,S2
				S
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51008BFP	············ 32pin		525mil SOP
M5M51008BVP,RV ············ 32pin			8 X 20 mm2				TSOP
M5M51008BKV,KR ············ 32pin			8 X 13.4 mm2 TSOP

APPLICATION

Small capacity memory units

PIN CONFIGURATION (TOP VIEW)

							NC
								1		32	VCC					ADDRESS
							A16
								2		31		A15 INPUT
							A14	3		30		S2				CHIP SELECT
							A12									INPUT
								4		29		W				WRITE CONTROL
							A7					A13				INPUT
								5		28
							A6					A8
								6	M5M51008BFP	27						ADDRESS
ADDRESS							A5					A9				INPUTS
								7		26
		INPUTS					A4					A11
								8		25
							A3								INPUTOUTPUT ENABLE
								9		24		OE
							A2					A10				ADDRESS
								10		23
							A1									INPUT
								11		22		S	1			CHIP SELECT
							A0				DQ8					INPUT
								12		21
							DQ1				DQ7
				DATA				13		20						DATA
							DQ2				DQ6
		INPUTS/						14		19						INPUTS/
OUTPUTS							DQ3
								15		18	DQ5					OUTPUTS
							GND				DQ4
								16		17
								Outline 32P2M-A
		A11			1												32		OE
		A9																	A10
					2												31
		A8																		1
					3												30		S
		A13			4												29		DQ8
		W			5												28		DQ7
		S2			6												27		DQ6
		A15			7												26		DQ5
		VCC						M5M51008BVP,KV											DQ4
					8												25
		NC																	GND
					9												24
		A16			10												23		DQ3
		A14																	DQ2
					11												22
		A12
					12												21		DQ1
		A7
					13												20		A0
		A6																	A1
					14												19
		A5			15												18		A2
		A4
					16												17		A3
						Outline 32P3H-E(VP), 32P3K-B(KV)
	A4																		A3
					16												17
	A5																		A2
					15												18
	A6																		A1
					14												19
	A7																		A0
					13												20
	A12																		DQ1
					12												21
	A14
					11												22		DQ2
	A16
					10												23		DQ3
	NC																		GND
					9			M5M51008BRV,KR									24
	VCC
					8												25		DQ4
	A15																		DQ5
					7												26
	S2																		DQ6
					6												27
																			DQ7
	W				5												28
	A13																		DQ8
					4												29
	A8
					3												30		S		1
	A9
					2												31		A10
	A11
					1												32		OE

Outline 32P3H-F(RV), 32P3K-C(KR)

NC : NO CONNECTION

1	MITSUBISHI
	ELECTRIC

1997-1/21 MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51008B series are determined by

a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps with

the low level S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input

OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H).

FUNCTION TABLE

Mode

DQ

ICC

S1

S2

W

OE

X

L

X

X

Non selection

High-impedance

Stand-by

H

X

X

X

Non selection

High-impedance

Stand-by

L

H

L

X

Write

Din

Active

L

H

H

L

Read

Dout

Active

L

H

H

H

High-impedance

Active

When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by

S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.

BLOCK DIAGRAM
			*								*
A4	8	16									21	13	DQ1
A5	7	15					SENSE AMP.				22	14	DQ2
A6	6	14	ADDRESS INPUT		ROW DECODER	131072 WORDS			OUTPUT	BUFFER	23	15	DQ3
A7	5	13				X 8 BITS					25	17	DQ4	DATA
				BUFFER		(1024 ROWS
A12	4	12				X128 COLUMNS					26	18	DQ5	INPUTS/
						X 8BLOCKS)								OUTPUTS
A14	3	11									27	19	DQ6
A16	2	10									28	20	DQ7
A15 31		7									29	21 DQ8
A13	28	4
A8	27	3
ADDRESS								DATA INPUT	BUFFER
INPUTS
A0	12	20	ADDRESS INPUT		COLUMN DECODER	CLOCK
				BUFFER		GENERATOR
A2	10	18
A3	9	17
A10	23	31
													WRITE
											5	29	W CONTROL
			ADDRESS INPUT										INPUT
A1	11	19		BUFFER	BLOCK DECODER						30	22	S1	CHIP
														SELECT
A11	25	1									6	30	S2
														INPUTS
A9	26	2												OUTPUT
											32	24	OE ENABLE
														INPUT
											8	32	VCC
											24	16	GND
													(0V)
* Pin numbers inside dotted line show those of TSOP
2						MITSUBISHI
						ELECTRIC

1997-1/21 MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

	Symbol	Parameter	Conditions	Ratings	Unit
	Vcc	Supply voltage		– 0.3*~4.6	V
	VI	Input voltage	With respect to GND	– 0.3*~Vcc + 0.3	V
				(Max 4.6)
	VO	Output voltage		0~Vcc	V
	Pd	Power dissipation	Ta=25°C	700	mW
	Topr	Operating temperature		0~70	°C
	Tstg	Storage temperature		– 65~150	°C

* –3.0V in case of AC ( Pulse width ≤ 30ns )

DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted)

Limits

-70VL, -70VLL

-12VL, -12VLL

Symbol

Parameter

Test conditions

-10VL, -10VLL

-15VL, -15VLL

Unit

VCC=3.3±0.3V

VCC=3.0±0.3V

Min

Typ

Max

Min

Typ

Max

VIH

High-level input voltage

2.0

Vcc

2.0

Vcc

V

+0.3V

+0.3V

VIL

Low-level input voltage

–0.3

0.6

–0.3

0.6

V

VOH1

High-level output voltage 1

IOH= –0.5mA

2.4

2.4

V

VOH2

High-level output voltage 2

IOH= –0.05mA

Vcc

Vcc

V

-0.5V

-0.5V

VOL

Low-level output voltage

IOL=2mA

0.4

0.4

V

II

Input current

VI=0~Vcc

±1

±1

µA

1=VIH or S2=VIL or OE=VIH

IO

Output current in off-state

S

±1

±1

µA

VI/O=0~VCC

Active supply current

ICC1

S1=VIL,S2=VIH,

20

35

15

30

(Min cycle )

other inputs=VIH or VIL

mA

Active supply current

ICC2

Output-open(duty 100%)

3

10

3

10

(1MHz)

1) S2 £ 0.2V

-L

60

55

ICC3

Stand-by current

2) S1 ³ VCC–0.2V,

µA

S2 ³ VCC–0.2V

-LL

12

11

other inputs=0~VCC

ICC4

Stand-by current

S

1=VIH or S2=VIL,

0.33

0.33

mA

other inputs=0~VCC

* –3.0V in case of AC ( Pulse width ≤ 30ns )

CAPACITANCE (Ta=0~70°C, unless otherwise noted)

	Symbol	Parameter	Test conditions		Limits		Unit
				Min	Typ	Max
	CI	Input capacitance	VI=GND, VI=25mVrms, f=1MHz			6	pF
	CO	Output capacitance	VO=GND,VO=25mVrms, f=1MHz			8	pF

Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 3V, Ta = 25°C

3	MITSUBISHI
	ELECTRIC